System Integration C++

Chen Liu’s resume

Phone: 971-***-****

e-mail:***********@*******.***

Knowledge and Skills:

Computer Architecture, both general purpose, and, especially, IA32 and IA64, embedded microprocessor architecture.

Storage, PCIe, USB protocols and peripheral devices.

Programming in C, C++, Assembly, C#, Java, Python.

Silicon Debug tools and methodology, Intel In Target Probe(ITP) and Trace Hub. Lauterbach debugger.

Software debug tools and methodology, Windbg and IDE debugger.

Full stack testing and validation, from feature requirements gathering, test designing and planning to test execution.

Mathematical foundation and data modelling.

Working Experience:

Feb. 1999—Nov. 2024, engineer at Intel Corporation:

June 2012 – Nov. 2024, System Integration Engineer at WSIV(Windows System Integration and Validation) in CCG(Client Computing Group).

Role and responsibilities: Develop Use Case System Integration Steps(UCISes), design and implement tests for validating the UCISes and functional requirements. Feature enabling at the power on of BayTrail(BYT), CherryTrail(CHT), Tangier(TNG), Broxton(BXT), Apollo Lake(APL), Cannon Lake(CNL), Ice Lake(ICL), TigerLake(TGL), TigerLake-H(TGL-H), Fish Haw Falls Workstation(FHF), Meteor Lake (MTL) and Granite Rapids Workstation(GNR-WS) as domain owner for Debug and Trace, Reset and Power Management, IO, USB Type-C, Storage and PCIe.

Developed and implemented plans and test procedures for integrating and validating systems, significantly reducing errors and improving quality.

Discovered, debugged and resolved numerous bugs. For example, an Intel CPU cache coherence bug during BXT power on, and a memory corruption bug on MTL, that silently corrupted code and data. Both bugs would have escaped which would result in product recall if not for my work, saved the company from the reputation damage and financial cost of billions of dollars:

Discovered, debugged and resolved Intel CPU cache coherence bug at Intel Broxton(BXT) platform power on. The root cause of the bug is that the CPU did not properly flush all internal buffers, queues and caches at the entry of reset. It instead saved them and restored them at the exit of reset. As Windows randomizes the kernel load address at boot, the restored data is stale and not correct. It turns out that many generations of Intel CPUs had been doing that until this bug is discovered and fixed on Broxton platforms.

Discovered, debugged and fixed an Intel platform memory corruption bug at Meteor Lake platform power on. Brief description: At every cold start, an MRC is run to tune setting parameters for memory, which are stored in registers for memory subsystem usage. Since MRC takes long time to run, the registers are saved at warm reset entry and restored at the warm reset exit so that MRC needs not be run at the exit of warm reset. The root cause of the bug is that these registers were not properly saved to persistent storage and was lost with more aggressive power management policy for warm reset. Hence the MRC parameter registers hold invalid values after warm reset. The problem can only be observed when memory corruption happened to key kernel data or code, causing system crash. Otherwise just quietly corrupting data/code, and hard to notice. As it is hard to catch, the probability is high for it to escape.

May 2009-June 2012 At Intel VTG(Validation Tools Group) as Intel silicon debug tool ITP (In Target Probe) Run Control developer.

Developed ITP releases, and successfully supported its use at the power on, for each of the following platforms: Valleyview(VLV), Haswell(HSW), Tangier(TNG) and Jaketown(JKT).

May 2007- Apr 2009 At Intel VTG OT(Observability Tool) team developing Low Level Software tools for controlling probes used in microprocessor and chipset debugging.

Designed and coded a 6-tab equalization algorithm using an FIR Filter, greatly improved signal responses for many systems.

Jan. 2006—May 2007. Intel OHT PCE Advanced Process Control (APC) developer.

Develop Process Control Systems (PCS) for semiconductor manufacturing processes.

Projects completed:

1.Developed MESAdapter, a COM server in C++ providing clients with interfaces for accessing MES300 objects such as Lot, Operation, Entity, PM and Product and their attributes, a component in the APC(Advanced Process Control) Framework 2.3 release, used by the ControlExecutor, ScriptEngine and APC applications.

2.Developed the Etch Bias 1.1, a feed forward and feed back APC control application, using SED(Spin, Expose and Develop) scanner data, DCCD(Development Check Critical Dimensions) and FCCD(Final Check Critical Dimensions) metrology data to determine the optimal Hardmask Etch time.

3.Developed the Post-Metro step of the CDO (Carbon Doped Oxide film) Feedback 2.0, a feed back control application using the metrology thickness data of the film to control the Carbon Doped Oxide deposition time.

4.Developed EFCC 2.0.6 for controlling the exposure and focus for SED(Spin Expose Develop) process. This release fixes the algorithmic error in the previous version that results in more than 1 milli-joule error in dose setting.

5.Developed SRC 2.1.7 to enhance the Stepper Registration Control with the capability of managing the wafer lots between the Stepper and Registration metrology tools.

6.Designed the Poly Etch PM Compensation control system. It uses the APC hard mask etch to compensate the CD differences resulted from a PM on the down stream Poly etch tool.

May 2003—Dec 2005 D1C Automation Station Controller Developer

Design, implement and support the Registration OVL(Overlay registration), DRSem(SRS Defect Review), FTM (Film thickness metrology), BSM(Back Side Metallization) and TCM(True Contact Resistance Measurement) station controllers. Won several awards, including a division award, for my contribution to improvement of the manufactory control system.

Projects completed:

Note: All station controller releases are COM-ATL applications coded in C++.

1.Developed 8 releases for OVL controller with features such as: CON-PLY-STR multi-layer measurement using PSM (Phase Shift Metrology) functionality for CON registration, OARS (OVL Automated Recipe Selection), E40/E94 Standards of Process Job and Control Job on OVL, etc. Won the LTD Division Award in 2004 for the implementation of PSM.

2.Developed Altreg 1.4 (a multi-regression registration control model) with Sample Plan measurement location validation, verifying that the locations measured by the Registration tool match that in the Sample Plan generated by ALD (Advanced Lens Distortion).

3.Developed the FTM (film thickness measurement) release ASET5_4.1.0fw1.5.3 implemented the support for CDO Feedback APC control system, and resolved the data corruption issue caused by the tool EC upgrade from sequential wafer processing to multi-chamber parallel wafer processing.

4.Developed the Defect Review Station controller DRSem_3.1.1fw1.5.3 and DRSem_3.2.1fw1.5.3 with new features such as Carrier recreate using RE-PROCESS host command, the Assist mode and assist level control, etc.

5.Developed a .NET application Log Analyzer in C#, enabling AIT engineers and fab technicians to view and analyze across the fire walls the log files generated by automation components.

6.D1C MES300 Integration test. Led a team of 4 test engineers to complete the tests for SAFT NTSC, FA300 RR server, APF, EC and RTS, and SAFT test for Sort. The tasks include planning, scheduling, providing technical support to team members, coordinating the resources and resolving all the defects with the product owners. Provided technical support to the product owner for the insertion of SplitChart 3.5 and LSF for NTSC FW2.x in D1C.

7.Developed NTSC Framework component WatchDog Actions for tool idle/error notification. Expanded the WatchDog capability with following new functionalities: 1) Publish to FabView Action. 2) Script Action. 3) Publish to Fame DB Action.

Dec. 2000—April 2003 Work at the Server Management group of EPG, the Enterprise Platforms Group

Designed, implemented and supported hardware diagnostic tools for Intel server platforms for managing Windows and Linux servers.

Feb. 1999—Dec. 2000 Work at PCO (Platform Compliance Operation, an organization under DAL(Desktop Architecture Lab))

Developed software for testing OEM’s Systems and peripheral devices for compliance to the PC99 and PC2001 System Design Guide. Authored and conducted industry wide review of specifications, designed and implemented tests in the technology areas such as power management, PCI, CardBus and ACPI. All the tests I created were included in the Microsoft WHQL HCT9.6 as part of Microsoft Windows Logo program.

May 1997—Feb. 1999, Software engineer at Micro Systems Engineering, Inc. (D&R division of Biotronik).

Developed control software for Cardiac pacemakers implanted in patients through wireless communications. Developed and released the firmware for a Cardiac Defibrillator implanted in patients to diagnose fibrillation conditions and to deliver therapies and shocks, using Motorola's 68HC11 micro controller, and Whitesmith's 68HC11 C Compiler and Assembler, EasyCase design tool and In-Circuit Emulators.

Organized with fellow engineers a self-study group studying neural networks and developed an AI tool providing auto diagnoses with the data from implant devices in place of physicians using neural network model.

June 1995--May 1997, software engineer at Inovec, Inc., a company started by fellow CIS graduates from University of Oregon. Built mathematical models for logs with data from laser scan devices, solution for cutting the log into boards maximizing the value of the log, and the program to control the sawmill machines to automatically cut the log.

OTHER EXPERIENCE:

Instructor and Graduate Teaching Fellow at the University of Oregon, Department of Mathematics.

EDUCATION:

M. S. in Computer and Information Science, University of Oregon, 1996, GPA: 3.84.

Ph.D. in Mathematics, University of Oregon, 1994.

M. S. in Mathematics, University of Oregon, 1992, GPA: 4.00.

ACADEMIC ACTIVITIES:

Invited speaker at the Special Session on ``Representations of Algebraic Groups and Quantum Groups'' of the 891st meeting of the American Mathematical Society at the Kansas State University, Manhattan, Kansas, March 1994.

Invited speaker at the Second Chinese National Algebra Conference in Chongqing, China, 1986.

PUBLICATIONS:

1.“Visualizing Logical Correlation In Trace Data For System Debug”, IEEE

Computer, Volume 54 Issue 3 (March 2021), 28--36.

2."Projective functors for quantized enveloping algebras", Communications in Algebra, Vol. 22 no. 6 (1994), 2125--2172.

3."The Adjoint Representation of Quantized Enveloping Algebras", contributed to the 891st meeting of the American Mathematical Society in 1994.

4."Tensor products of finite and infinite dimensional representations of quantized enveloping algebras", Ph.D. thesis, University of Oregon, 1993.

5. "On generators and relations of simple groups of Lie type", J. Math. Research & Exposition 1988 No.3, 349--357.

6. "On the root system and the commutator formula of twisted groups”, J. of Xiangtan University No.2, 1986, 54--63.

REFERENCES:

Upon request.

End of Chen Liu's resume.

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