Firmware Development Engineer

Fuad Mert Tokad

*** **** **.

San Francisco, CA *4131

Phone: 415-***-**** - mobile

E-mail: ******@*********.***

Experience:

Jun. 2022 -

Jun. 2024

Softworld, Inc. Waltham, MA

Position: Contractor for Granite EPIK as Sr. MoIP Firmware Engineer, R&D group.

• Developed a voice-band soft-modem module executable on the software-defined telephone stack employed on Epik system in compliance with ITU V.22bis standard.

• Reverse engineered a voice-band modem based protocol (modem3e) between alarm panel and controller unit. This involved decoding of the Bell.103 FSK modem signaling.

• Assisted with various connectivity issues encountered at customer side. C-code is used for the software development.

Mar. 2021 -

Jun. 2022

Pyramid Consulting, Inc. Alpharetta, GA

Position: Contractor for Accenture as Firmware Lead Engineer Worked directly with Meta (Facebook) engineering team in validation efforts of various SoC products.

• Porting various third-party firmware drivers to customers embedded AR/VR platform. Firmware development in C-coding.

• Pre-/Post-silicon verification of driver functionality. Synopsys HAPS and Zebu systems are utilized for pre-silicon testing.

Nov. 2011 –

Mar. 2020

Macom Technology Solutions / Applied Micro Circuits Corporation, Santa Clara, CA

Position: Principal Design Engineer, Connectivity Group

Verification and initial platform firmware development for ARM Cortex-M3 embedded microprocessor on a PAM4 based 100G optical transceiver chip. QA test development in Python.

FreeRTOS evaluation for future version of the transceiver chip.

Firmware development for the multi-channel MACsec PHY chip: Auto-Negotiation

(AN) and KR-training firmware for SERDES ports operating at 10G-100G rates. Programming in C using Keil development environment for the embedded 8051 microcontroller.

DSP training firmware for a 40G transceiver test chip. Chip initialization and DSP training control algorithms coded in C (ported from Python scripts) compiled for a 32-bit Tensilica (Cadence) embedded microcontroller.

Firmware development for 10G-BaseT Ethernet PHY chipset with embedded 32- bit Tensilica microcontrollers. Responsible for processor configuration, developing low- level drivers and overall firmware build process, including: Verification of processor environment and related sub systems on RTL test-bench Boot-loader firmware, EEPROM image generation with configuration data and CRC Driver development for the embedded 1G-BaseT IP core and performance optimization for connections over long CAT-5 Ethernet cables.

Also worked with the Processor Group, developing various firmware functions, such as RAPL (Running Average Power Limit) for the ARM "Server-on-a-chip". Feb. 2011 –

Nov. 2011

Micrel Inc, San Jose, CA (now part of Microchip Technology Inc.)

Position: Staff Applications Engineer responsible for the support of Ethernet chipsets supporting Precision Time Protocol (PTP), based on IEEE 1588 spec.

Testing and verification of the PTP protocol executing on an ARM based processor sub-system.

Independent Contractor

Design and development of a microcontroller based iPhone / iPod accessory unit.

Firmware development for Microchip PIC18 8-bit microcontroller.

Circuit design and PCB layout

Feb. 2007 –

Aug. 2010

Plato Networks Inc, Santa Clara, CA

Position: Sr. Staff Firmware Engineer. Initial firmware engineer responsible for the definition and implementation of the microcontroller based system firmware for the company’s 10G-Base-T Ethernet chip.

A Tensilica embedded 32-bit RISC processor core is used for controlling entire functionality of the chip.

Developed firmware for calibration of analog circuits, auto-negotiation and for the training sequence state-machine as outlined in the IEEE 802.3an specification.

Developed diagnostics features for test and evaluation of analog circuits and Digital Signal Processing (DSP) blocks in the system.

RTL verification of the DSP blocks with firmware support before the tape-out.

Full chip system verification firmware for the RTL test-bench.

Firmware development setup (with JTAG Debugger) and test environment setup for the chip evaluation board.

Work closely with analog and digital circuit designers as well as system engineers in verification of functional blocks and development of the full functional firmware. Oct. 2005 -

Oct. 2006

Texas Instruments, Sunnyvale, CA (contracting through Netpolarity Inc, San Jose, CA)

Position: Contractor, Residential Gateway Embedded Systems (RGES) division, ADSL DSP software group.

RTL verification of the next generation ADSL CPE chipset on FPGA platform. Bringing up the 320c6xx DSP core on FPGA with conventional development tools (Code Composer Studio) through JTAG interface. Validate and debug other ADSL related signal processing blocks on the FPGA platform.

Developed DSP code for testing the packet interface (ATM-TC) block between DSP and the Network processor.

Verification of the DSP core's cached memory subsystem. Assisted in development of a new Code Composer Studio driver for the DSP.

DSP firmware development for the ADSL chip: implemented new functions and ported existing code in C and assembly (ASM code) using the FPGA platform and the Palladium emulator system.

Jan. 2000 -

Jan. 2005

Centillium Communications Inc, Fremont, CA (VoIP group was later acquired by Transwitch Corporation)

Position: Staff Engineer, Networking Business Group.

Has been instrumental in bringing up several versions of the Entropia high- capacity voice-over-IP (VoIP) chip, focusing on the embedded DSP core. This chip contained eight DSP cores with co-processors.

Developed platform firmware for supporting the debugger software using the SPI serial port.

Firmware development in ASM code for the proprietary VLIW type DSP core.

Implemented new features, both in data-flow control and signal-processing areas. Solely responsible for bringing-up and initial VoIP firmware development for the P400 ADSL CPE chipset. Ported entire CO DSP firmware developed for Entropia to P400. Translated the code for cached-memory architecture used at the CPE chip.

Developed and implemented Caller-ID receiver firmware. Nov. 1997 –

Dec. 1999

Altigen Communications Inc, Fremont, CA

Position: Sr. Design Engineer. Responsible for firmware development for the companies TMS 320c62xx DSP based communication boards.

Helped the company to establish a DSP firmware development platform. Implemented signal-processing algorithms including FSK modem for Caller-ID transmission and detection. Converted telephony firmware/algorithms from TI’s 320c5x DSP to 320c62xx DSP family. Evaluated and integrated the G.723.1 compression software on the company’s communication board platform.

Also involved in digital design by programming a Xilinx FPGA using Verilog HDL. Has designed and simulated the serial communication link for accessing the Analog Codec and the “ring generator” circuits for a new telephony card.

Accomplished various other tasks such as testing, board-level hardware debugging, etc. during employment.

Jan. 1996 –

Nov. 1997

S3 Incorporated, Santa Clara, CA

Position: Senior MTS. Member of an ASIC design team developing an audio/modem IC. Responsible for design, implementation, verification and gate- level synthesis of the serial interface to an external AC’97 compliant analog CODEC. The circuit functions include sampling-rate conversion and related digital filters.

Verified the functionality of a TMS 320c5x compatible DSP core with VHDL simulator. Developed test codes in assembly to be executed on the simulator. Floreat Inc., a subsidiary of S3 Incorporated, Saratoga, CA

Involved in company’s high-speed modem projects, including the ITU (CCITT) V.34 standard. Worked on both DSP code development and Hardware system designs incorporating TMS320c5x series and other DSP platforms. Jan. 1992 -

Jan. 1996

UTI Design Corporation, San Jose, CA

Position: IC-Design / DSP engineer. Founding member of this small startup company, spun-off from Seponix Corporation. Initially continued with fax-modem chipset development later functioned as a contracting IC-development company, mainly for Maxim Inc. Major accomplishments include following:

Development of both DSP firmware and demonstration code executing on an 8031 type host microcontroller for UTI’s own V.17 fax modem chip-set. A TMS 320c25 DSP was utilized.

Developed DSP code for the V.29 fax + V.22bis data modem project based on a TMS 320c15 and realized a full functional breadboard using FPGA’s.

Complete design of two CMOS DC-to-DC converter (charge-pump) ICs, which has been manufactured on different processes. Responsible for entire design procedure including schematic entry, analog (Spice) simulation and layout with DRC and LVS check.

Redesigned a popular bipolar FSK demodulator/Tone decoder IC (XR2211) using a smaller geometry bipolar process, thus reducing its die-size.

Reverse-engineered a CMOS battery-charger IC, proved the functionality of its digital circuitry by simulation, and involved in the redesign. Jul. 1988 -

Jan. 1992

Seponix Corporation, San Jose, CA

Worked as IC Design / System Engineer on both DSP code development and Analog Front-End (AFE) design of the V.29 and V.17 facsimile modem chip-sets. Mar 1987 -

Jan. 1988

Biltam Corporation, Istanbul, Turkey

Worked as engineer for the installation and maintenance of data communication and network equipment.

Education:

M.S.E.E. from Middle East Technical University (METU) in Ankara, Turkey. Thesis work involved the theory and implementation of the "Trellis Coded Modulation", utilized in high- speed modem applications. This method was realized at Seponix Corporation for the V.17 chip-set. (Jul. 1991)

B.S.E.E. from Technical University of Istanbul (ITU), Turkey. (Feb. 1987) Summary of Qualifications:

Strong background in telecommunication systems and digital signal processing (DSP). C and ASM programming for embedded systems, Python. Worked with ARM Cortex, Tensilica, 8051, TI 320x series processors. Working experience with 100G-10GBASE KR, 10G-Base-T Ethernet PHY, ADSL and V.xx voice-band modem standards.

VoIP development experience on systems and chipsets. Digital and analog IC design experience from design to layout. Experience with FPGA based system development.

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