Design Engineer Physical

Sachin Jain Email: ***********@*****.***

Phone:789-***-****

SUMMARY

2.5 years of experience as ASIC Physical Design Engineer.

Good knowledge of entire aspects of physical design flow from Net list to GDSII.

Responsible for block implementation from synthesis followed by floorplan, placement, CTS, Routing, Extraction, Static timing analysis & signoff flows, Physical verification.

Experience in solving setup timing closure in synthesis and timing constraints changes.

Effective in placing macros and performing sanity checks.

Capable of analyzing HFNS during Placement. Effective in timing driven and congestion driven placement. Effective in congestion removal techniques by using placement blockages and keep out margins.

Capable of analyzing skew optimization during CTS and taking care of signal integrity issues like Crosstalk, Reliability issues like Electro-migration, IR.

Hands on experience in sign off checks like LEC, DRC & Extraction, STA and LVS.

Having good Knowledge in Perl and TCL scripting. TECHNICAL SKILLS

● Tools : ICC2, DC, FC, Prime Time and Cadence Virtuoso, Mentor Graphics, CRO, DSO, Calibre

● Technology Node : 6nm

● Software Skills : UNIX, TCL, Perl

Professional Experience:

• Currently working as a Physical Design Engineer in the position of Silicon Design Engineer 2 at AMD India Pvt Ltd, Hyderabad from July 2023 to till date.

• Worked as an Intern in Physical design domain at AMD India Pvt Ltd, Hyderabad from June - 2022 to May-2023.

PROJECTS

Project 1: Block Level Implementation (PNR, ECO)

Block 1:

Technology : TSMC 6 nm

Instance Count : 535k

Macro Count : 18

Clock frequency : 685.4 MHz

Challenges faced :

The main challenge which I faced is in placing the macros to overcome the timing violations, to resolve this issue, perform various floorplan experiment placed the macros manually using a hierarchy bycoloring, fly lines.

Block 2:

Clock frequency : 463 MHz

Instance Count : 547k

Macro Count : 1

Block 3:

Clock frequency : 115.5 MHz

Instance Count : 3.5k

Macro Count : 6

Challenges faced :

Main challenge which I face is to restrict the presence of Spare cells in the left, top and right side of pads which causing LUP’s violations.

Applied partial placement blockages in left, top and right side of pads to resolve the issue. Responsibilities:

Executed PNR flow starting from Synthesis, floor plan, power plan, placement, CTS and routing.

Experience in solving setup timing closure in synthesis and timing constraints changes.

Arriving at best floor plan based on timing, congestion & DRC. Tried different floor plan experiments to get the better QOR.

Placed the macros according to the guidelines and module hierarchy without any Base DRC.

Written multiple ECO’s to fix DRV, Setup, Hold and noise violations. Used all possible methods like cell swapping, sizing, Skewing, adding buffers and cloning.

Techniques that I used to improve the CTS ID are Multi point CTS and placing the root buffers Nearer to the logic.

Verified all the sign off checks like IR Drop, LEC, LVS, DRC's and STA.

Port locations provided by chip top were resulting in minimum spacing violation and shorts, provided the feedback and resolved by moving ports to available tracks.

Met Targeted ID by using Macro modeling and MPCTS.

Fixed Electro Migration Issue By using layer hoping and Parallel Routing

Fixed Antenna violation by using Metal jumpers.

Done Manual Routing to clean DRC and LVS violations. Project 2: Perl based project

Write a Perl script to perform the task of separating the waived and nonwaived errors and warnings from total, error and warnings of specific targets like (Synthesize, Place, Cts, OptCts, Route, OptRoute, ReRoute).

For completing this script, I create a control file where I give the name of all the targets, path of reference waived errors and warnings, path of output files, and run area. Project 3: TCL based project

1)Write a Tcl script to create partial placement blockage around all the TMAC’s cells in the design in which for first 2 microns around TMAC's cells I have to give 80% blockage and for next 5 microns I have to give 50% blockage.

Since TMAC's cells are present in design in pair form like In the pair of 2 cells, 4 cells, 6 cells like that, so the main issue which I face is how to find out from all TMAC's how many pairs are created and how to get the BBOX coordinate of these pairs, to resolve this issue I use the command create_geo_mask.

Create_geo_mask command creates a new geo_mask object and returns a collection that contains the new object. geo_masks represent polygonal regions of arbitrary angularity and can be used for geometrical computation.

By using create_geo_mask command and their attributes, I get the number of pairs of TMAC's cells present in the design and their BBOX coordinates.

2) Write a Tcl script to create partial placement blockage around all macros and create routing blockage over DTCD cells.

Project 4: EEG based project NIT Warangal

Key Skills: Verilog

EEG stands for Electroencephalogram. It is a painless test that measures the electrical activity in the brain.

Implement brain connectivity parameter measures xyz in verilog using Phase Lag Index matrix data as input. Ported the design to FPGA board and tested successfully using vio module. EDUCATION

M.Tech -VLSI System Design: (2021-2023) From NIT Warangal with an aggregate of 6.96 CGPA.

B.Tech -Electronics and Communication Engineering: (2016-2020) From Maulana Azad National Institute of Technology Bhopal, with an aggregate of 7.58 CGPA.

Intermediate/+2: 2015 Board of Secondary Education MP From Lucky Brilliant Public School Indore with an aggregate of 82.8%.

HONOURS AND ACHIEVEMENTS

Gate 2020, AIR 1266

Scored all India rank 9570 out of 0.15 million students in JEE (advance) – 2016.

Scored 213 marks and hence all India rank 14616 out of 0.15 million students in JEE

(mains) – 2016

EXTRA CURRICULAR ACTIVITIES

Worked in an NGO-AAROHA

Member of ROBOTICS CLUB MANIT

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