Engineering Intern Design Engineer

MEHMET CETIN

*********@****.***********.*** linkedin.com/in/m-cetin 559-***-**** Fresno, CA (open to relocate) SUMMARY: FPGA engineer with 3+ year of hands-on experience using a range of technologies and programming languages. SKILLS

• Languages: Verilog, SystemVerilog, Python (Programming Language), C++

• FPGA Simulation and Verification Tools: Intel Quartus Prime, Modelsim, Xilinx Vivado

• FPGA Board: Xilinx Artix-7, STM32 ARM Cortex-3

• Communication Protocols: JTAG, UART, USB A to B 2.0 EXPERIENCE

Electrical Engineering Intern, Jun 2023 - Nov 2023 Modesto Irrigation District Modesto, CA

• Assisted with model verification of the system to improve its efficiency

• Arranged electrical monthly peek data to meet requirements of the distribution system

• Helped to update fee associated with different services

• Documented and compared generator interconnection costs from various electric utilities

• Documented work-flow process to obtain a better working system in the utility Integrated Circuit (IC) Design Engineering Intern, Jun 2022 - Aug 2022 Vishay Siliconix San Jose, CA

• Monitored analog/mixed-signal circuits resulting in the creation of a test bench approved by Senior Design Engineer

• Designed numerous cells (ADC, DAC, oscillator, delay, comparator, R-ladder, multiplexer, schmitt trigger, and bandgap circuits) using Mentor Graphics Calibre and Cadence Virtuoso

• Fixed bugs and errors in cells by utilizing Verilog, VerilogA, and VerilogAMS

• Simulated and verified designs to assure that simulation waveforms are correct

• Documented results of the Verilog View and the Schematic View

• Practiced Unix and Linux commands to use virtual computer EDUCATION

California State University, Fresno, Fresno, CA Dec 2024 Master of Science - Electrical and Computer Engineering Related coursework:

• Advanced VLSI Circuits and Systems (RTL, Analog Circuit Design and Verification)

• Advanced Hardware Design of Computer Arithmetic (RTL, Digital Circuit Design and Verification) Pamukkale University, Denizli, TR Jun 2020

Bachelor of Engineering - Electrical and Electronics Engineering PROJECTS

Low-Clock Latency SDRR-Based AES

• Developed an optimized implementation of AES-128 encryption using double-rate registers to enhance security.

• Analyzed the security and performance of the AES cryptography algorithm and improved it by 25%.

• Implemented the design on a Xilinx Artix-7 FPGA development board.

• Used Chipwhisperer-pro to perform Side-Channel Attack for security monitoring.

• Xilinx Vivado is used for FPGA prototyping.

• Jupyter Notebook with Python scripts is used for Side-Channel Attack.

• Submitted to the IEEE International Symposium on Circuits and Systems (ISCAS) for peer review, highlighting the project’s significance in the field of cryptography and secure FPGA design ( https://2025.ieee-iscas.org/ ). Frequency Efficient Design for a Digit-Serial Polynomial Basis Finite Field Multiplier Using Factoring Technique

• Designed and implemented different bits of adders such as 4-8-16-32 bit by using Verilog.

• Utilized the Synopsis Design Compiler and compared them with each other with regard to the area, delay, and power, resulting in the smaller design implemented, the more efficient results obtained.

• Utilized Cadence Innovus tool for floor planning, place, and route.

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