Embedded Linux System

Resume of:

John Meisner

SUMMARY: Over ** years of engineering, engineering management and contracting experience including analog / digital hardware as well as embedded system firmware design.

HIGHLIGHTS:

●Co-inventor on Excimer Laser Control System patent

●IoT new product development

●Extensive experience in new product embedded system development including Intel/Altera and AMD/Xilinx FPGAs using VHDL, microprocessors (ARM-based) using “C” mainly and in system architecture design.

●Managed / designed data acquisition systems for Industrial, Medical, Military, Environmental and Commercial technologies.

●Extensive Embedded Linux Experience including Yocto and Petalinux

●Designed and tested circuitry in a DSP-based modem for satellite communications.

●Areas of contribution range from high level design feasibility studies and specification preparation to low-level design and test of hardware and firmware, to customer support and interface.

EXPERIENCE:

Contract Position (Onsite) Denso 9/23-1/24

V2X (Vehicle-to-Everything) - Improved functionality using C / Embedded Linux / Yocto toolchain

Implemented / Enhanced Web GUI (CGI)

oLogin Authentication Security Feature

oDisplay Build Information

Implemented System Service

oNetworking using SNMP protocol

oLocal Event / Fault Logging using syslog

Created / Utilized Build Scripts

oPython

oBash

Enhanced PAM-aware (SSH) application for advanced security

Contract Position (Onsite) Evident Scientific 10/22-4/23

NDT Array failure testing with real-time display

Developed Embedded Linux image using Petalinux / Yocto toolchain

Developed / modified kernel drivers, user space API and test scripts for new product features

Used Xilinx Zynq Ultra-scale FPGA using Octavo SIP to develop Vivado .xsa for Vitis Platform creation

Wrote Diagnostic tests in C using Vitis IDE platform BSP / API for new board bring-up

oEthernet

oUSB C

oSD Card

oGPIO

oDisplay Port

oMemory Peek / Poke (using Vivado Register Map or Direct Memory)

Debugged peripheral probing problems as well as Device Tree preventing product startup

Interfaced with HW / System engineers for new embedded C applications.

Wrote Python Test Scripts

Contract Position (Remote) Shield AI 3/22-7/22

Drone Auto Navigation using Embedded Linux image processing using Nvidia platform, Nuttx Rtos sensor processing with embedded C/C++ / STM32F4 processor

Wrote Bash scripts for Secure Boot / key handing

Wrote Python build scripts for Nvidia Linux Build

Used Nuttx RTOS to acquire / process Sensor streams

Wrote C code for Sudden Power Loss

Contract Position (Onsite) ATEC Spine 11/21-3/22

Sr Firmware Consultant

New Product Software Development involved in Embedded Linux Development

●Embedded Linux Application / Yocto / BSP development

●USB / Wifi communication to host

●Laird Wifi driver development

●Logging

●RabbitMQ client

●WiFi setup using Python

Contract Position (Hybrid On/Offsite) – FastDetect, Pasadena CA 04/21- 10/21

Sr Embedded Engineer

New Product Software Development involved in FERN Full Stack IoT design – (Firebase Express React Nodejs) & End to End Integration Testing

●New feature development in C, NodeJS/React.

●Bare-Metal programming on NXP-1768 for Management of Optics, Motor and Thermal subsystem.

●MCU-RPi Protocol Verification/Update

●Error Handling

●Embedded Linux Boot, Services, Serial Driver, Device Tree Debug

●RPi interface to Google Cloud using GCPublisher functions.

Contract Position (Remote) - Ossia Inc Bellevue, WA 11/20 – 3/21

Sr Embedded Engineer

Activities: C, CLI, GUI, Addition of various Application Utilities / Features

Hardware: STM32H745 MCU, Raspberry Pi 4 SBC, TI CC2652 MCU

Tools: IAR EWARM, Confluence, JIRA, BitBucket, CubeMX

●Wrote Embedded C applications and utilities for RF Power Transmitter MCU

●Added new feature to debug MCU, 802.15.4 / Zigbee Proxy and receiver code.

●Extended logging function

●Extended FreeRTOS and UART / RS232 CLIs

●Added features to FreeRTOS Control task

●Added WDT cause of reset feature.

●Worked on Raspberry Pi Message Manager interface to STM32H745 MCU (SPI bus)

●Debugged system temperature command from MCU via SPI to Antenna Management ASIC

Contract Position - Analog Devices Inc, Wilmington, MA 7/19 – 12/19

Sr Embedded Engineer

Activities: Verilog, C, CLI and GUI, Secure IP

Hardware: MAX 10, Analog High-Precision Parts

Tools: Intel Quartus Prime, ModelSim, JIRA, BitBucket, LabVIEW RTE, Eclipse IDE

●Complex Impedance Analyzer

●Added new feature to debug POSIX-based CLI engine written in C and interfaces to User GUI

●Secured Max 10 IP using AES128 binary encryption

●Processed Front-end Data to determine complex I/Q vectors

●Analog Interface via Verilog engine mainly via SPI

●Wrote Nios II application in C using HAL API POSIX-like interface to HW

●On-chip RAM and Flash with instant-on flash configuration

●Wrote engine for character mode interface to CLI (debug) and LabVIEW GUI (customer)

Meisner Consulting – Various projects, Del Mar, CA 7/18 – 6/19

Sr Electrical / Embedded Engineer

Activities: VHDL, C, Python, and Golang development of IoT Router / Devices for BLE / 802.15.4

mesh

Hardware: ARM Cortex-M / A, Raspberry Pi

Tools: GNU Radio, Xilinx Vivado, PetaLinux, Intel Quartus II, OrCAD, GitHub

Various IoT projects involving HW: Digital, Analog and PCBA design; SW: Linux drivers, distributed

control / mesh network C and IoT Router Python / Golang, etc.

Automated Controls Development in C for a Xilinx Zynq 7010 SoC using PetaLinux.

Legrand - Wattstopper, Carlsbad, CA 4/16 – 6/18

Sr Electrical Engineer/Sr Embedded Engineer

Activities: IoT Device for Building Control System Development

Hardware: ARM Cortex-M / A, Microchip ECC508A

Tools: Altium, GCC, Linux, IAR IDE, Eclipse, Bitbucket, C, Go, Python, PHP, Linux

IoT Lighting System Development

●HAL Implementation with C and Micro-Chip CryptoAuth Lib. New secure, wireless product line for IoT application

●IoT Router Certificate Tracking System Using PHP, Ajax jQuery, Lighttpd, Sqlite3, Debian Linux deigned a system to “harvest” devices at Manufacturing Facilitate then update a local DB and update Device Registry Manager in Azure Cloud

●Linux-based Data Processing Device Investigated a Python Message Bus / Linux Ubuntu System to replace existing design

●IoT Gateway Used Go to satisfy A POC for a sequential concurrent processing system using Dell Gateway 3001 and Ubuntu Core 16

●IoT Edge Device Development ARM M0 embedded design of a DALI Bus controller using C

Philips Medical Sys, Carlsbad, CA 9/12 – 2/16

Sr Electrical Engineer

Activities: Ventilator System Prototype Development

Hardware: TI Stellaris ARM Cortex-M uC, NXP i.MX 51 SOC, Linear Tech PMIC using SMBus,

SPI, I2C

Tools: ORCAD Capture, Pads Board Layout, Xilinx ISE FPGA, Actel FPGA, ThreadX, UBoot

Next Generation Ventilator

●System Integration and Debug: HW / SW / System debug and wrote HW Test using C++. Included UBoot bootloader, Power Management, Blower Motor Control, CBIT, POST, HW / SW system analysis, prototype debug, etc.

●Software Verification: Implemented HW and SW tests to assist in ventilator SW verification.

●System Reliability: Assisted in reliability tests SW / HW to validate long-term reliability

●System Startup Problems: Worked with SW engineers to resolve boot problems

Embedded System Development Consultant Retail Inkjet Solutions – CA 10/12 – 3/13

Activities: New Embedded Design Functionality

Hardware: Altera Cyclone IV, SPI, I2C

Tools: ORCAD Capture, Altera Quartus II, SOPC Builder and Eclipse, Python, Git, Tcl

●Inkjet Cartridge Electrical Test

●Embedded Design Improvement: Re-designed HW / FW to add new Electrical-Test functionality using VHDL and C. InterNiche Technologies TCP/IP Protocol Stack, Micrium uCOS II RTOS API and Altera Nios II processor were used.

●Services included were:

oTransaction processing by embedded TCP server sent from remote TCP client (host; Python).

oEmbedded digital and analog HW interfacing using I2C / SPI and transaction processor HW (i.e.., in VHDL)

oDUT data processing / control

oRemote configuration by embedded TFTP server from remote client; flash file transferred to RAM then to flash using Virtual File System

oTest command processing from remote Telnet client using embedded Telnet server

Sr Principal Engineer CareFusion - San Diego, CA 2012 to 2012

Activities: Board Design, Digital and Analog Power Management, Medical - New Infusion Pump R&D, New Rack Power Management Architecture Design, Test FW in C

Hardware: TI MSP430, Linear Tech PMIC using SMBus, RS485 IRDA, SPI, I2C

Tools: ORCAD Capture, Allegro Board Layout, C Language, IAR IDE (for test code

development)

●Next Generation Infusion Pump (Trident)

●Rack Management Board Design: Generated functional requirements / specification, block diagrams, power tree, I/O map for SW and power flow and startup analysis. Generated schematic, BOM and worked with PCB designers to generate layout. Required extensive interaction with Pro E engineers for packaging. Wrote prototype test plan and performed HW verification using IAR debugger

Embedded Design Engineer VII General Atomics - CA 2006 to 2012

Activities: System, Digital Analog HW and Embedded SW Design for Radiation Monitoring

Devices

Hardware: TI MSP430; NXP LPC2478 Altera Cyclone II; Zigbee Radio

Tools: Mentor Graphics, Matlab; Altera Quartus II / SOPC Builder; ICAP4 Simulator; C Language; Rowley Assoc Crossworks and Keil IDEs; SafeRTOS; Perforce and Visual SourceSafe SW CM

●Next Generation RMS System Design

●RM2020: Worked as part of a SW development team to design / test next generation RMS. Wrote SW to perform Power-On-Self-TEST (POST), initialization, flash interface for persistent data, continuous self-test and power-down ISR using "C" and SafeRTOS for LPC2478 ARM-based processor.

●RM3000: Proposed next-generation design using Altera Cyclone II SOPC and multiple soft Altera Nios processors utilizing switched fabric communications. Included new system / PWA testing concepts to reduce labor costs. Main design goals were: 1) reduce overall cost, 2) upgradeability, 3) eliminate / minimize part obsolescence problem, 4) provide high-speed platform to handle new detector processing.

●New Electronic Dosimeter Designs

●DoseGard5: Developed SW for new DoseGard5 battery-operated dosimeter. Used MSP430 and "C". SW Tasks included: 1) SyRS and SRS, 2) wrote SW Development Plan, 3) wrote scheduler, detector interface, RTC, POST and background self-test, user interface, calibration, IR command interface, writing / reading to / flash and error handling modules, 4) Interfaced with Marketing, Testing and SW QA

●Envirogard: Sole Design Engineer for new MSP430-based electronic dosimeter design. 1) System: Generated SyRS and FAT testing plan. 2) HW: Designed PWA for "novel" sensor and interface electronics including digital and analog circuitry. 3) SW: Wrote all SW including user interface, task scheduler, serial interface, detector signal processing algorithm, flash interface, RTC interface as well as multiple SPI and IC2 interface modules using "C".

●RM2014: Sole design engineer assigned to develop low-cost replacement for existing analog design. 1) System: Generated Development Plan to meet ATP requirements and worked with ME to design enclosure 2) HW: Designed new PWA including mainly digital circuitry 3) SW: Wrote all SW including detector serial interface, Touch Screen interface, RTC interface, task scheduler, flash interface, detector processing, analog output and display options using "C".

●RadMinder: Finalized design / development of ZigBee / Tiny OS based remote data collection design prototype which communicated to website via Global Star transmitter. Included were: 1) design digital interface to satellite transmitter, 2) modified FW to extend battery lifetime, 3) Calibrate / test system which included wireless sensor / bases station and satellite transmitter and data-collection website.

Staff Digital Electrical Engineer Northrop Grumman Corp, Inc - San Diego, CA 2005 to 2006

Activities: Digital Hardware and System Design, VHDL

Hardware: Xilinx FPGAs / CPLDs, PCI Express, 100 Mbps Ethernet, SW Defined Radio (SDR)

Tools: Mentor Graphics, Matlab; MATHCAD; Model Tech Model Sim VHDL simulation; Xilinx ISE; Synplify Pro; Synchronicity Design Sync

●SDR Digital Transceiver Design:

●Member of team to generate new spec for AMF project.

●VHDL

●Generated spec, design document and then wrote VHDL code to implement Synthesizer low-level control. Setup Phase Locked Loops (PLL) and Direct Digital Synthesizer (DDSs). Serial commands received from Local RF Control block of FPGA were decoded / implemented. Tested / debugged. Synchronicity Design Sync used to release code. Xilinx XPLA3 CPLD used.

●Generated spec, design document and then wrote VHDL code to implement Tuner low-level control. Serial commands received from Local RF Control block of FPGA were decoded / implemented. Synchronicity Design Sync used to release code. Xilinx XPLA3 CPLD used.

●Generated spec, design document and then wrote VHDL code to implement Digital board low-level control. Provided control / reset register interface to PPC440 processor, means to load configuration data directly into Virtex4 FPGA, means for PPC440 to write FLASH / load into FPGA and means to adjust JTAG chains for test. Synchronicity Design Sync used to release code. Xilinx XPLA3 CPLD used.

●Performed verification of part of main FPGA code which implements PCI / message router / Ethernet interface.

Senior Control HW Manager and Senior Electrical Engineer Cymer, Inc – CA 2002 to 2005

Activities: Analog and Digital Hardware Design and Design Management, Control System Design,

Laser Metrology Design

Hardware: CPCI, CAN bus, Altera and Altera FPGAs / PLDs, Xilinx FPGAs

Tools: Altera MAXPLUS II, ORCAD Capture, Pspice; Matlab; MATHCAD; Model Tech Model Sim VHDL simulation; Xilinx ISE and Foundation; Synplicity; Wind River visionCLICK Debugger; Lattice IspDesignExpert

●Re-designed Photodetector Module (PDM) to extend dynamic range and improve sensitivity to low fluence laser output pulses. Analog electronics modified to increase charge gain. Digital electronics interface changed to allow automatic PDM type determination, reduce noise contribution by synchronizing switching power supply clock and improved external synchronous link.

●Re-designed Photo-diode Array (PDA) Data Acquisition Module to extend dynamic range, improve bandwidth calculation, enhance resolution, and improve PDA control to allow optical integration for next generation laser design. PowerPC MPC823 processor for data processing / calculations; Altera 7K CPLD for front-end interface, 20 MSps ADC and 16-bit DPRAM to transfer frame data to CPLD.

●Conducted new DUV sensor investigation to determine whether BT-CCD, NMOS PDA, CMOS PDA or luminescent screen / visible sensor (i.e., FI-CCD) would be used for next generation laser wavelength / bandwidth metrology.

●Involved in Laser Control System architecture design including high bandwidth RS422 data acquisition and low bandwidth CAN bus, choice of CPCI backplane, power supply, DIO, and analog output boards for Control module. (Listed as co-inventor on patent.)

●Design of Timing and Energy module, which acquired laser pulse energy and timing measurements (jitter less than 200 psec) used in energy and timing control algorithms. Module communicated over 10 Mbps link to Control Module and a 20 Mbps to Photodetector module. Xilinx Spartan device used for interfacing.

●Involved in the design of laser safety system module that ensured laser could not fire when interlocks not satisfied. Communicated with Control Module using CAN bus and a Phytec Single Board Computer (SBC). Utilized Xilinx XCS200E FPGA and Altera 7K PLD to interface with SBC and input circuitry, respectively.

●Generated EMC design guidelines for use by all module designers.

Senior Electrical Engineer Veeco Instrument, Optimag Div - San Diego, CA 2001 to 2002

Activities: Analog and Digital Hardware Design, Embedded System Firmware Design, FPGA Design using VHDL and AHDL

Hardware: Altera FLEX 10K and MAX7K, Lattice 2064, Cypress EZ-USB 8051

Tools: Altera MAXPLUS II, ORCAD, Capture, Pspice and Layout; PCAD Schematic; Matlab; MATHCAD; Leonardo Spectrum; Model Tech Model Sim VHDL simulation; JTAG programming; Xilinx Spartan II

●Designed and tested high-throughput Deep UV auto-focus camera using a 1Kx1 CMOS Imager sensor, USB interface to PC, sensor signal processing using an 8051, sensor data acquisition using a 7K FPGA and VHDL and sensor control using a Lattice 2064 PLD. Involved sensor selection to meet imaging specs, prototyping and final board layout. This design was part of an optical inspection system.

●Re-designed a preamplifier card to reduce noise to 2 UV rms, increase resolution to 20 bits and determine / implement DC removal. Involved addition of FLEX 10K FPGA to digitally process data at the "front-end", interfacing with PC Digital IO Card using SPI, implementation of a 24-bit Sigma Delta ADC and 16-bit DACs. Code implemented using VHDL. This card was part of a quasi-static tester using magneto-restrictive effect. Required board prototyping and final design layout / testing. FPGA change to Xilinx Spartan II device was investigated.

Electrical Engineering Lead 4D Neuroimaging - San Diego, CA 2000 to 2001

Activities: Analog and Digital Hardware Design, Electrical System Analysis, Embedded System Firmware Design, FPGA Design

Hardware: Altera FLEX8K and APEX20K, VME Bus, Motorola 68040 CPU Boards, TMS320C40/TMS320C60, Lattice 1032, Ethernet, IP mods, Xilinx Virtex

Tools: Altera MAX PLUS II and Quartus; ORCAD Capture, Pspice, Express Layout; Matlab; MathCAD; Synario

●Responsible for the electrical design for a medical data acquisition / imaging product. Managed other electrical engineers and coordinated design work.

●Incorporation of delta encoding data compression with oversampling into data acquisition system to improve dynamic range. VHDL used for implementation in APEX20K200E device including use of some Altera LPMs JTAG port used to provide ISP and easier debug / test. Included board design modification and PCB layout. Analyzed effect of roll-over and effect on data quality.

●Front-end analog processing simulation for Intrinsic System Noise study using Pspice. Considered 1/f and white noise inputs and system transfer function. Investigated analog hardware modifications to reduce system noise.

●Involved in many electrical system issues including electrical safety testing, grounding / shielding, EMC compliance review and selection of UPS.

●Upgraded VME-based data acquisition system to latest Motorola CPU board. Board ran PSOS real-time operating system and obtained code via ethernet link. Data passed to CPU boards using IP modules.

●Modified FIR filters (TMS320C40) to adjust breakpoint and sample rate for high data rate acquisition. Investigated the upgrade of DSP boards from TMS320C40 to TMS320C60 DSP. Feasibility study for use of Xilinx Virtex FPGA instead of DSP including timing analysis and implementation issues.

Consultant - Meisner Consulting Corp - San Diego, CA 1999 to 2000

Activities: Analog and Digital Design and Analysis

Clients:

* Embedded Technologies Inc.

* Provided technical support for 1553 bus tester proposal for Avionics

* Provided technical support for Focal Plane Array Tester - high speed data acquisition

* Designed electronics for motor starter for climate control system

* Sorrento Electronics Inc.

* Analyzed / re-designed preamplifier to improve performance and reduce noise susceptibility

* Analyzed field installations of DSP based mixed analog / digital radiation pulse processing system to verify signal integrity and performance

Electrical Engineering Manager Nautronix, Inc - San Diego, CA 1997 to 1999

Activities: Analog and Digital Hardware Design, Power and Pre-Amplifier Design, Embedded System Firmware Design

Hardware: 68HC05, PIC16C74, DSP56001, Altera FPGAs (EP910 and EP7032S)

Languages: C, Assembly, LabView, ABEL, VHDL, AHDL

Tools: Altera MAX PLUS II, ORCAD Capture, Pspice and Layout

●Managed the electrical engineering team for underwater acoustic comm product.

●Designed a signal conditioning card that processed low level signals from an acoustic transducer. Included tasks were active bandpass filter design, Sigma-Delta ADC interface circuitry design, auto calibration and inter-card and parallel test port interfacing using an Altera 7K CPLD. Prepared board specification verified analog front-end using PSPICE simulations and verified CPLD design using MAXPlus II simulations.

●Re-designed a battery operated C (i.e., 68HC05 and PIC16C74) controlled beacon which acquired and processed acoustic data. Included tasks were amplifier current limiting, CPLD re-design to reduce battery current draw and design modifications to prevent inadvertent C resetting.

●Developed company grounding and shielding design guidelines.

●Re-designed transmit amplifier to improve transient response and to avoid transformer saturation.

●Resolved display driver and serial communications problems in a distributed processing acoustic positioning system.

Principal Engineer General Atomics - Sorrento Electronics - San Diego, CA 1988 to 1997

Activities: Analog Hardware Design, Firmware Design, Radiation Detector Design and Electromagnetic Compatibility Design

Hardware: 8086, 8051, 8031, 80960, TMS320C31

Languages: C, PLM/86, 8086 and TMS320 Assembly, ABEL

●Radiation Monitoring Systems

oRe-designed radiation detector interface HW / SW. Included digital pulse processing (TMS320C31), digital logic and front-end analog filtering design. Implemented "state of the art" DSP concepts to permit real time pulse

●EMI/RFI Compliance for New / Old Product Design

oResolved RFI and EMI sensitivity problems as company lead engineer

●Multi-Function RADIAC

oRe-designed and tested a battery operated microcontroller (8051) based neutron probe design. Included a high gain wide bandwidth amplifier re-design.

●Primary Nuclear Instrument Design for Seawolf Sub

oDesigned detector interface HW / SW

Staff Engineer

M/A - Com Linkabit, Inc - La Jolla, CA 1984 to 1988

Staff Engineer General Atomics - La Jolla, CA 1978 to 1984

Draper Lab Fellow / Research Assistant

Charles Stark Draper Labs - Cambridge, MA 1977 to 1978

Education

●M.S. in Nuclear Engineering, M.I.T. (thesis not completed) - Boston, MA

●B.S. in Electrical Engineering, Northeastern University - Boston, MA

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