Product Development Electrical Engineer

JEFFERY A. SMITH

Senior Electrical Engineer FPGA

***********@*****.***

I am a self-motivated, a good communicator, and quick to adapt. I have 20+ years of FPGA with VHDL development. I did high speed board design the first half of my career. I have 25+ years in the full spectrum of product development including proposals, requirements, architecture, trade analysis, digital design, FPGA design, verification, integration, and production transfer. I have developed FPGAs for Satellites, Space Launch Vehicle, Motor Control, Digital Radios, Industrial, and Telecom. I developed an FPGA for the Internal Space Station, Soft Capture FPGA, which aligns capsule on entry. My Goals are to have some fun, contribute to the team, and support product development. Not Interested In Relocated. SKILLS

• Education: Bachelor of Science, Electrical, Rochester Institute of Technology, GPA 3.63, with Honors.

• FPGA HDL Development SME: Develop full FPGA process Requirements to HDL to place and route implementation. Many lessons learned with constraints, multiple clock domains crossing, and timing analysis. Developed DO254 safe state machines. Develop reusable IP. Implemented Microsemi RAD Hard RTAX, Xilinx Vivado, Altera Quartus. Implemented high speed FPGA LVDS interface, ADCs, DACs interfaces.

• FPGA Verification SME: Verify at the top system level, developing reusable self-checking interface models. Develop Bus Functional Models to emulate CPU, DAC, and ADC interfaces. Use VHDL real time to create advance models. Develop reusable checkers to self-check real time data. Verify data with files or Computational models, Verify functional and post place and route timing simulation.

• FPGA Algorithms SME: I worked with Scientist and System to develop fix point models in MATLAB Simulink. Fix point models are an efficient means to develop bit resolution and range for FPGAs. Highly skilled with MATLAB Verifier, verifying algorithm HDL comparing to fixpoint and floating-point models’ side by side. I did this on International Space Station Soft Capture FPGA, controlling eight actuators. It worked first time. Also, worked with Xilinx System DSP developing algorithms.

• FPGA Process SME: Developed FPGA Process, tailoring from large Safety Critical to small Proof of Concept. Participated in DO254 with B737 and Airbus. I can streamline a cost-effective Process.

• Competent Team Leader: Group Management, delegation, tracking, coaching, motivation.

• Accomplished Requirements Manager: Capture, architecture, manage, link, and trace.

• Proficient Digital Designer: CPU, DSP, High Speed, ADC, DAC, Opamp, LVDS, DDR, LDO, Layout

• Some Embedded Software Programmer: Micro, PICs, DSP

• Tools: Miocrosemi Libero, Xilinx Vivado, Synplify Pro, MATLAB-Simulink, MATLAB HDL Coder, MATLAB HDL Verifier, QuestraSim, Hyperlynx LineSim & BoardSim, Orcad Capture-Layout-Pspice- Timing Designer, Doors, LINUX, SVN, GIT

References Available upon request

WORK EXPERIENCE Continued on next page

Sept 2023 to Present, Senior Digital Engineering- RTX Collins I worked on DO254 certified programs, requirements, design, Doors, Jama, SVN, JIRA, tracing, reviews, DO-254 AC 20-152 COTS IP documentation and reviews.

Nov 2018 to Sept 2023, Senior Digital Engineering- L3Harris I worked on large teams and small teams developing Satellite Imaging and GPS FPGAs. Developed VHDL models and self-checkers for verification. Self-check setup and hold time. Refined post place and route simulation. Used Microsemi Libero for RTAX, Vivado for Xilinx Ultrascale. Implemented high speed FPGA LVDS interface, ADCs, DACs interfaces. Skilled at Cross domain Clocking. I mentored young Engineers. As Senior SME I am called in when projects have issues, typically multi-clock domains, constraints, and timing analysis. Nov 2006 to Nov 2018, Senior Digital Engineer- Moog I develop Space Launch Vehicle FPGAs, generating requirements, complex design, extensive verification. I have extensive experience with MATLAB HDL Verifier, co-simulating VHDL with Simulink models, some C code. I convert S domain, floating point to Z domain, fix point models. Run trade analysis defining architecture and performance dynamics. Develop model-based designs with MATLAB HDL Coder, and Xilinx System Generator. I create complex verification systems with self-checking testbenches utilizing reusable bus functional models, procedures, and real time library. I created Requirements with Customers and Systems, manage, link, and trace the requirements to verification, using Doors. I championed FPGA Process, reviewing DO-254, 498, NASA TOR2006 creating standards, templates, and reuse libraries. I lead project teams, delegate tasks, define gateways, track, and provide estimates. Implemented DO254 with B737 and Airbus.

Dec 2005 to Nov 2006, Digital Engineer, Northrup Grumman Amherst I developed a defense Industry, high-speed DSP TMS320C6415, circuit board with high-speed Altera stratix EPS80 FPGA interfacing with 256 MHz DDR LVDS ADC, DAC, and opamp analog circuits. I used Hyperlynx LineSim and BoardSim to thoroughly analyze the signal integrity, defining termination resistors and transmission analysis and proper board stacking as well as trace layout.

Jan 2003 to Dec 2005, Electrical Engineer, Contractor I developed variety of designs in the Defense, instrumentation, Industrial Controls, and Point of Sales industries. I found it exciting to design diverse digital Boards and FPGAs. I developed DSP and CPU designs ranging from tiny instrumentation to large industrial Controller. This includes developing support functions such as Opamp signal conditioning using Pspice, ADC/DAC interfaces, power supplies, LDO, switches, and variety of communication ports, UART, CAN, and Ethernet I captured schematics, created BOM, procured parts, managed layout, program, and transfer to manufacturing.

Jan 2001 to Jan 2003, Senior Development Engineer, Vanteon Consultant I developed an Industrial PC motherboard with Intel 66 MHz 486, 100 MHz PCI interface, flash boot ROM and hard drive interface. Developed FPGAs for telecom and an Industrial. Aug 2000 to Jan 2001, ASIC Design Engineer, Xerox Office System Group I developed ASIC for color copier image functionality. Developed ASIC and testbench input jpeg image forward correction algorithms and output jpeg.

May 1995 to Aug 2000, Electrical Engineer, Microwave Data Systems Developed Digital Radio Boards and FPGAs working with RF Engineers. Support Manufacturing, handoff, and debug

Contact this candidate