Solutions Architect Program Management

TRANG VU

Renton, WA ***** ******@*****.*** 206-***-**** (Cell)

SR. VALIDATION ENGINEER

POWER PERFORMANCE MANAGEMENT CLIENT/SERVER ARCHITECT HARDWARE SYSTEM ENGINEER Proven an innovative, solutions-focused senior engineer and creative problem solver with an eye for details and accuracy. Leverages in-depth experience in Power and Performance debugging, developing, and validating computer hardware new technologies. Ability to effectively work with cross teams, social, self-driven, focus who reacts well to changes in a fast-paced environment. Exceptionally skilled at system validation planning, budgeting, identifying, developing, testing, and debugging issues. Competencies include: Server/Surface System/Device Validation/Verification Power Management Cloud, Security, & Virtualization Intel SoC Compatibility Test Automation Analysis Issues PROFESSIONAL OVERVIEW

HCL/Microsoft Corporation

Sr. Tech Lead Engineer Power and Performance, contract position (May 2018 – July2024) System low power enabling in Surface end-to-end programs.

• Develop system low power savings features to address new changes opportunities.

• Define and coordinate HW, SW, board, device requirements to deliver low power features score that meet product needs.

• Lead HW low power subsystem metrics Surface devices to optimize power/performance delivery.

• Manage progression/regression debug efforts to root cause feature sequences function/device bugs and silicon bugs caused by interactions between hardware and software.

• Deliver Power Ramp-Up to new hire Power engineers and new design validation power team in India.

• Ability to work with open ended problem statements from larger data set of telemetry.

• Implemented ever first the Brown-Out Protection technology in Surface Tablets and Laptops.

• Developed driver tools to aid measurement of system Low Power Consumption.

• Deep dive into schematic and board Power signals and adapt into correct Power State focus. HCL/Microsoft Corporation

Sr. HW Design Verification Engineer, contract position (April 2016 – Oct 2017) Verify and debug new technologies Surface devices and play a role in validation activities on fast paced multi products design team.

• Lead system validation focus into authenticated connection, trackpad, keyboard, I2C, Power.

• Deep dive into Oscilloscope, Power supply, Multi-meters, PCB board, robotic tools.

• Developed data collection macro to analyze and verify metric data against Spec’s requirements. It resulted in saving team’s math lab license and efficiently saving time cross sea teams.

• Developed intensive test matrix patterns for Surface Host System’s Connection and Authentication resulted in effective verification and closer to zero bug zone.

• Wrote up test Spec, a new method C Sharp Connection testing on Surface Pro devices.

• In depth troubleshoot, debug, and collaborate with internal/external members to root cause issues. Intel Corporation

Sr. Validation Engineer (2002- July 2015)

Trang Vu

******@*****.*** 206-***-**** (Cell) Page 2 of 2 Effectively planned, developed, and executed validation projects to accelerate product development and improve the quality, reliability, and compatibility of Intel Xeon Server platforms.

Lead, defined, developed Power/Performance and CPU test plan across multiple Intel Server projects in both manual focus and automation server system environments.

Provided technical expertise, and gave consultation supports in Power Management, Performance, Security, and CPU areas.

Lead and defined unique Server Usage Testing Models including Cloud, Network, Clients, Storage, Database, multi-task Servers and estimated allowance budget on hardware IO technologies including PCIEs, switches, USB, SSD, SATA HD.

Analyzed and debugged Data Center, Client, or Automotive use cases with emphasis on silicon energy efficiency and server reliable.

Lead and enable Power-On Server efforts enable Intel Server Platform to first boot across multiple OSs.

Managed new validation team cross-site Santa Clara, CA in High-Performance Computing focus into validation plan and debug skills.

Worked on confidential Government/Intel project pre-silicon Simic’s environment. Component Design Engineer (1996- 2002)

Developed and lead Perl language automation validation regression tool to build, release, and execute daily chip model into all defined test use cases.

Provided 24hrs tool support to design teams chipset E870.

Managed cache and memory areas include injecting and handling errors in testing.

Debugged and analyzed daily failures to support the next day silicon model release. TECHNICAL SKILLS

Operating Systems: Windows, Linux, Red Hat, CentOS

Language and Scripting: C#, PowerShell, Perl, Python, ITP

Versioning Control: MS build, Git

Virtualization Tools: Hyper-V, VM Ware

Hardware: Platform, PCB board, schematic, firmware, logic analyzers, Oscilloscopes, JTAG

System: Architecture, memory, cache, PCIE, USB, SSD, Switch, BIOS, UEFI, drivers, debugs

Server Datacenter: Cloud, Network, Power, Performance, RAS, Storage, Database, Security ACADEMIC CREDENTIALS

Bachelor of Science, Computer Engineer UNIVERSITY OF WASHINGTON; SEATTLE, WA Master Project Management COLORADO STATE UNIVERSITY; GLOBAL CAMPUS

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