Technical Manager Process Control

Crystal Maddix

**** ** **** ******, ********, OR 97211

503-***-**** • **********@*****.***

EXPERIENCE

WaferTech, LLC (TSMC Subsidiary) Camas, WA 2000 – 2013

PROCESS INTEGRATION TECHNICAL MANAGER 2009 - 2013

Chairman of Fab Change Control Board

oReview fab process change proposals and results for release

oWorked with modules to safely & quickly bring up tools for ramp production

Department Contact / Representative for

oStatistical Process Control

Worked with owners for key reductions in k-shifted parameters to prevent fab scrap

oScrap Reduction

Managed task force to reduce RcVia outliers

oMfg Productivity

Evaluate process limitations to determine which are necessary for quality production and which are unnecessarily limiting production capacity

Liaison with Training for Engineer Development

oDevelopment of New Engineer Training

oAttended training and Implemented new K-T problem solving class

oCoordinated and Ran Domain Knowledge training and testing in SPC/FMEA/Kepner-Tragoe

Led Special Customer Risk Ramp

oIntensive in line and offline review to successfully run volume production without yield / process window confirmation

oRecord yields and well controlled electrical data from newly ramped products

PROCESS INTEGRATION SECTION MANAGER 2006 - 2009

Managed Small Technology Logic Group of 6-8 engineers

oHighest WIP products in fab

oCoordinated daily priorities for sustaining and new products

oCo-work with modules & mfg to efficiently run quality product

oSearch for process weakness from yield and electrical data

Identified RTA monitor weakness impacting high value resistor, resulting in new methodology fanned out to as BKM to all TSMC fabs

Transferred 0.16 µm MM / 0.14 µm Logic and 0.18 µm HV technologies to F11 from mother TSMC Fabs

oDefined Process window

oMatched Inline / Offline performance to mother fab

oModified process for unexpected mismatch

HDP dep pump size difference leading to metal clipping and new recipe development

0.16 µm MM metal line optimization due to small photo process window on shrink technology

Fab to Fab alignment on currently running 0.18 µm Technology

Production Ramp of 0.16 µm MM & 0.14 µm Logic Technologies

oAdditional tool matching and release

oYield / WAT control optimization

Handled Fab Excursions

oVBD Failures which impacted all customers / all technologies

Correlated to implant process tool which was contaminating wafers

Worked with equipment engineering to identify potential contaminant and source within chamber based on defect location and possible failure modes

oCustomer Specific Issues:

Identified and worked with photo process to correctly monitor photo tools with stray light issue causing LDD scumming and Cp failure on specific products

oBPTEOS Weakness Event impacting all customers / technologies

Led team to identify BPTEOS process weakness, develop appropriate control limits on monitor to prevent future excursion

Worked with customer engineering and customers to contain and evaluate impacted material

PROCESS INTEGRATION ENGINEER 2000 - 2006

Yield Enhancement

oKLA-Tencor Defect Analysis

Sustaining 0.35 µm / 0.25 µm Logic & SRAM and 0.18 µm MM & Logic Technologies

oInvestigation and Resolution of Electrical testing and Yield issues

oDevice Characterization to identify & improve process margin

Team Member of 0.15 µm Logic Technology process transfer team

oProcess window definition

oInline / Offline process matching

Continuing Process Development of 0.25 µm 6T SRAM

oYield improved from 20% to 80% with ILD optimization

MAD HANNA 2013-2022

Bar Owner/Operator

oManaging/Hiring/Scheduling Staff

oOrdering

oBartending

oLicensing/Payroll General office management

ANALOG DEVICES 2022 - 2023

PROCESS INTEGRATION ENGINEER

Team Member of 0.18 µm BCD / Logic Technology process transfer team

oProcess window definition

oInline / Offline process matching

oInvestigation and Resolution of Electrical testing and Yield issues

oDevice Characterization to identify & improve process margin

*Note gap between previous employment due to care for family member

EDUCATION

Oregon State University, Corvallis, OR

Master of Science, Electrical Engineering, 2000

Major in Material Science / Minor in Fabrication

Masters Thesis – “Novel Phosphor Development for Alternating-Current Thin-Film Electroluminescent Devices”

Oregon State University, Corvallis, OR

Bachelor of Science, Electrical Engineering, 1997

References2;

Tsung Kuo – Former President/Fab Director Wafertech {TSMC} ****@****.***

Wen-Han Juan –Director Process Integration Engineeer Wafertech {TSMC} *****@****.***

Bin Teck Soh – ADI *******.***@***.***

Jim Wu Senior – Process Integration Engineeer Wafertech {TSMC} ****@****.***

Paul Schuele – CTO Sharp Corporation ********@*****.***

Curtis Tsai – Intel Corporation ***********@*****.***

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