David Fatzer

Boulder, CO/Huntsville, AL.

david.fatzer@gmailcom

Embedded design engineer focused on FPGA/RTL/SoC and schematic/PCB design.

Bachelor’s degree in Electrical Engineering.

Master’s degree in Computer Engineering.

Principal Skills:

RTL/SW Design

FPGA RTL/SoC design. Xilinx, Intel and Microsemi devices. CPLD design.

FPGA development using Vivado & Quartus. Linux/Windows environments.

VHDL, Verilog, UVVM, embedded C++ & Python. Modelsim & Questasim.

Zynq Ultrascale+, Artix-7, Spartan3/6/7, Intel Arria, Max. Xilinx PS configuration.

Embedded processors: Microblaze, PowerPC & Arm-Cortex

Complex proprietary IP core design and COTs IP core integration.

Image processing algorithms using C++ & VHDL.

Video interface: DisplayPort (PS), LVDS Display & VGA (PL)

FPGA SerDes configuration. 8B/10B protocol. PRBS7 BERT.

Slow serial protocols: UART, SPI, I2C, 1-Wire, ARINC-429, MIL-STD-1553B

Multiple clock-domain designs. Elastic buffering. Handshaking.

Test bench design and documentation. Self-checking tests. Test Procedure Specification

HW test bench design using C++ & Python.

Git version control system. Branching.

PCB Design

Schematic entry: OrCAD, DxDesigner. PCB layout tools: Expedition.

High-speed, high-density PCB design. Reliability classes 2 & 3.

PCB layout specification: Stack-up, impedance, blind, buried and micro vias.

Multi-gigabit serial protocols: Fibre-Channel, Ethernet, PCI Express, SAS/SATA

Large multi-core processor & FPGA designs. Up to 22 layers.

DDR2/3/4 memory. Gigabit serial links.

Video interface phys: DisplayPort, LVDS Display, VGA

UART, SPI, I2C, 1-Wire.

Signal integrity simulation using HyperLynx. (Supervisory)

Functional circuit simulation using LTSpice and Simulink.

Data acquisition. Small signal sensor analog. RTD & thermocouple. Linearization.

POL power supply design & simulation. MIL-STD-704

Design for manufacturing.

General

Documentation and presentation using Visio, Word, Excel, and PowerPoint.

Design to requirements. Requirements traceability. Concurrent design & documentation.

Embedded software design. C++/UML, bare-metal and RTOS. Not embedded Linux.

Good understanding of OO concepts. Classes, inheritance & polymorphism.

IP cores include:

Image processing:

a.RGB/YCbCr conversion.

b.YCbCr to JPEG file compression.

c.Scaling and rotation.

d.Overlay & alpha blending.

e.Speckle removal.

f.Background color homogenization.

AC RMS meter. Synchro-to-digital converter.

Slow serial protocol IP including UART, I2C, MDIO and SPI.

Two functioning versions of PIC microcontroller and 8051 IP cores.

SATA SS disk drive controller SoC. “Drive Message Router”. (Using SATA link-layer core)

Patent pending. Application number 14/684,105 “Drive Message Router”.

November 2022–Present Norwix Inc., CT (Contract)

Board and FPGA Engineer. Orcad & Vivado

Project: Zynq Ultrascale+ board design. Consolidate legacy 3-board design into one board.

Upgrade FPGA to Zynq Ultrascale+. POL supplies. JTAG, UART & I2C.

USB2 Host Hub, Gigabit Ethernet, SD Card, DisplayPort, LVDS display, DDR4 memory.

RTL Analog Input State Machine.

32 inputs, 500KSps, software configurable prioritizing sampling schedule.

A/D converter SPI interface.

Software configurable UV & OV thresholds with hysteresis for each channel.

Zero-register BRAM implementation.

All sampling and thresholding managed by RTL FSM. Values read from BRAM.

Imported legacy code into new design.

Replaced two Spartan-7 FPGAs by migrating their IPs into the Ultrascale+.

Implemented serial IO to reduce FPGA pinout requirements.

LVDS Display Driver.

Xilinx AXI Video DMA CNTLR transfers video from DDR4 to serializer.

4-lane 7:1 serializer, LVDS drivers.

Vitis bare metal Zynq c++ software configures AXI Video DMA CNTLR.

Improved design of legacy DSP RTL.

PC board layout supervision.

March 2022 – November 2022 Sphere One Tech, Fairfield, CT (Contract, Remote)

FPGA Engineer

Project: ASML max contract duration reached.

Continued to work for ASML as co-developer through Sphere One Tech.

Oct 2020 – March 2022 ASML, Wilton, CT (Contract, Remote)

FPGA Engineer

Project: FPGA Implementation of Serial Communications with White-Light Laser

Intel Arria FPGA. Quartus Development System

Responsible for:

a.Top-level design

b.Sub-module specification

c.VHDL coding

d.VHDL test-case specification. Test coding. Self-checking test bench

e.Specified and coded Bus Functional Module of Laser for integration into UVVM environment.

f.Requirements traceability matrix.

Project: Porting of existing functionality to another PCB platform with different IO circuitry

Intel Arria FPGA. Quartus Development System

Responsible for:

a.Top-level design, including melding of target system acquisition firmware with legacy functional firmware

b.Concurrent firmware development and testing task division.

c.VHDL design coding

d.VHDL test-case specification. Test coding. Self-checking test bench

Dec 2019 – Sept 2020 Teradyne, North Reading, MA (Contract)

PC Board Electrical Engineer

Project: PC Board Design

ADC, DAC, I2C, SPI, PWM, tach, RS232, 1-Wire & POL design.

Integration with Zynq controller board. (Zynq board outsourced).

Design Validation Test design and execution.

Vivado SoC VHDL/SDK C++ Test Firmware and Software design. December 2017 – May 2019 Curtiss-Wright, Santa Clarita, CA (Contract)

Senior Electrical Engineer

Project: Abrams Ballistic Computer Upgrade Schematic & FPGA Design

Radiation-hardened design.

Single board computer design consisting of:

1.Dual core 64-bit PowerPC processor.

2.DDR3L memory on board.

3.Dual Artix-7 FPGAs. One SoC, general purpose. One MAX 10 system controller.

4.COTS PCIE-to-VME & MIL-STD-1553 IP core.

5.FPGA SoC design in VHDL using Vivado.

a.AXI4 bus based SoC

b.PCI Express interface to PowerPC

c.PowerPC master parallel bus interface to AXI.

d.ADC & DAC sampling with priority scheduling. BRAM based.

e.FIR filter implementation.

f.Parallel Flash and NovRAM interfaces.

g.Gigabit Ethernet Interface (Xilinx IP)

h.MIL-STD-1553 (COTS IP Core)

6.Dedicated FPGA hosting COTS PCIe-to-VME64 core.

7.Verification using VHDL/QuestaSim. Self-checking tests.

8.POL power supply design & simulation.

June 2017 –November 2017 General Dynamics, Minneapolis, MN (Contract)

Avionics Engineer

Project: Avionics Module Design (PC Board Design)

CPU/DSP board consisting of:

1.12 core Intel Xeon processor.

2.4 channels of DDR4 operating at 2133 MT/S.

3.2 Xilinx Ultrascale FPGAs with Zync processors.

4.PCI Express Gen 2 & 3. 10 & 40Gbit Ethernet.

5.Altera maintenance and power sequencing FPGA.

6.High-power point-of-load power supplies.

Responsibilities:

1.Schematic design.

2.Power supply design.

3.Component placement, PCB stack-up specification and routing strategy development.

4.DDR4 & gigabit communications routing.

5.Maintenance FPGA HDL & embedded software specification.

November 2011 - February 2017 – Spectra Logic Inc. (Boulder, Co.)

Senior Electrical Engineer

Projects:

Design verification of a 6Gbps multilane SAS server/JBOD hierarchy. Performed throughput measurement resulting in the reconfiguration of gigabit lane topography.

Standard Gigabit Ethernet switch with bridges to CAN and UART ports. Spartan-6 based FPGA SoC. RTL and C++ firmware. DDR2 memory.

Proprietary, FPGA-based Ethernet switch. Custom hardware transport layer eliminates the store-and-forward latency accumulation associated with long chain network switch topologies. Inherent hardware redundancy eliminates the need for Spanning Tree Protocol. Bridges to CAN, I2C and UART. Microblaze-based SoC & Verilog on Xilinx FPGA.

Proprietary, FPGA-based SATA SS disk drive controller. Patent pending. Custom IP core implements a one sector SATA drive for passing messages from a server, down a multi-level SAS hierarchy, to a SATA endpoint. Permits in-band communications with proprietary control endpoints anywhere along the SAS hierarchy. Verilog and C++ firmware.

AC/DC converter. Custom 600W power supply replaces legacy GE supply. Form fit and function compatibility requirement. Includes power factor correction and current sharing among multiple units. Based on TI power factor control and resonant converter reference designs.

Responsibilities include:

PC board schematic design and layout supervision

C++ DSP code for power factor control

C++ DSP code for resonant converter control

Control loop modeling and simulation in Simulink

EMI compliance

I2C Communications

2008-2011 – Advanced Energy Inc. (Fort Collins, Co.)

Projects:

High-speed industrial communication board design (EtherCAT). FPGA SoC based.

Responsibilities include:

PC board schematic design and layout supervision

Embedded software design and documentation

Prototyping of both ASIC and IP-core based versions

Integration with existing proprietary products

Test and demonstration PLC software including GUI

Developing software techniques to optimize throughput

Communication upgrade to existing power supply product line.

Responsibilities include:

Architectural update from distributed intelligence to single FPGA SoC solution

High-Speed DDR2 memory implementation

High-speed analog to digital conversion

Embedded software design and documentation

FPGA VHDL design using Aldec Active-HDL

Multi-gigabit fiber optic custom communication protocol design (2.5Gbps)

Board to board high-speed LVDS communications

Hardware digital filter design (VHDL)

PC board schematic and layout including multi-gigabit routing

2006-2008 – Imaging Business Machines LLC. (Birmingham, Al.)

Project:

High-speed image frame grabber with integrated hardware processing and compression.

The unit collect continuous image data from a single-line scanner, processes the image to improve legibility, compresses it and makes it available to a host via PCI Express. FPGA implemented on a Xilinx Virtex FPGA.

Responsibilities include:

System-level design

Research and development of image processing algorithms

Software simulation of image processing algorithms

RTL/VHDL implementation and simulation of image processing algorithms

PC board schematic design and documentation

PC board layout including multi-gigabit routing

Hardware components include – PCI Express, CameraLink LVDS interface, DDR2 SDRAM, Point-of-load power supplies.

FPGA image processing cores include:

JPEG color compression engine

Adaptive threshold algorithm

Image de-speckling and enhancement

Document boundary detection

Image scaling and de-skew

Barcode reader

Above cores implemented and simulated in Visual C++ prior to migration to VHDL coding

2000-2006 - Sanmina-SCI (Huntsville, Al.)

Projects:

1Gbps Fibre Channel Communications Card for the Apache Helicopter

Responsibilities include:

Board-level hardware schematic design and PCB layout supervision

C software for message router (Intel i960 processor).

Hardware/software debugging & integration

Bit error rate testing.

Customer interfaced during system integration.

MIL-STD-1553 serial interface

Responsibilities include:

Incorporate an off-the-shelf Mil-Std-1553 serial interface IP core into an avionics unit to permit communications with 1553-compliant devices.

Avionics Interface Unit (AIU)

Responsibilities include:

System-level design of multi-board data acquisition unit.

Board-level hardware and FPGA design for main controller board.

FPGA design for I/O controller board.

Personally proposed, researched and realized Sanmina’s first SoC design.

FPGA IP cores include – AC RMS meter, Synchro-to-Digital converter, UART.

Avionics Display Unit

Developed image processing FPGA code for demonstration and presentation to the Army.

Responsibilities include:

Board-level hardware specification.

Board-level and FPGA firmware simulation.

FPGA IP cores include:

FPGA IP cores for geometric bi-linear scaling and rotation.

Digital camera interface.

NTSC video output.1994-2000

1994 – 2000 Computrols Inc. (New Orleans, La.)

Project: Hardware and embedded software design of a series of networked control units for high-rise building automation.

Units include:

HVAC controller

Magnetic & proximity access controllers

Communication with networked smoke detectors

RS232 multiplexer/de-multiplexer over fiber optic converter

RS485 network line repeater

Reverse engineered and implemented several communications protocols.

Education:

University of Alabama at Huntsville

Master of Science in Computer Engineering, August 2005.

Concentration: FPGA design.

Designed, coded and tested synthesizable versions of the 8051, PIC16 and PIC18 processors.

Designed working IEEE-754 compatible floating point IP core.

Published paper on PIC16 IP core development. Presented paper at the 2003 IEEE Computer

International Conference on Microelectronics System Education in Anaheim California.

Completed 57 hours of graduate-level courses. GPA: 3.833

University of New Orleans

Bachelor of Science in Electrical Engineering May 1985.

EE GPA: 3.97, Perfect GRE math score: 800 out of 800.

Completed 27 hours of graduate level courses with a graduate GPA of 4.0.

Contact this candidate