Concepts

• Computer Architecture: DRAM, Cache, Cache Coherence, Virtual Memory, Pipelining, Pipelining Hazards, Scheduling, Data Path and Control, Data Hazards, Branch Prediction, Concurrency and Synchronization.

• HDL: System Verilog, Finite State machine, Assertions, Constraint Randomization, Functional Coverage, Bus Functional Models, OOPs, UVM, Testbench Environment

• Static Time Analysis, Retiming, Advanced Modelling Issues, Hardware Arithmetic, Delays, Transient Analysis, Logical Effort SAKET SWAMI

Portland, US Email: adzvv1@r.postjobfree.com Phone: +1-971-***-**** LinkedIn: saketswami Objective

Ful-time in VLSI - Digital IC Design / Verification / Validation starting August 2023. Education

M.S. Electrical and Computer Engineering ( GPA 3.30 / 4 ) Sept 2021 – Jun 2023 Portland State University, Portland OR

Relevant Courses

- Microprocessor System Design

- Computer Architecture

- Advanced Computer Architecture I & II

- ASIC modelling and Synthesis

- Digital Integrated Circuit Design

- System Verilog

- Fundamentals of Pre-Silicon Validation

- Post-Silicon Validation

- High Performance Digital Systems

- Python Scripting

B.Tech. Electronics & Telecommunication Engineering ( GPA 3.58 / 4 ) Aug 2017 - May 2021 Vishwakarma Institute of Technology, India

Technical Skills

Programming languages SystemVerilog, Verilog, UVM (Basics), Python, C/C++, Assembly(x86/MIPS) Computer-based Tools Mentor QuestaSim, Xilinx Vivado & ISE Design Suite, Synopsys Design Compiler, Matlab-Simulink, PyCharm IDE

Operating Systems Windows, Linux

Work Experience

Intel Corporation - Verification Engineer: GPU Hardware PPA Intern, San Diego US Jun 2022 – Dec 2022 GFX Shader ASM Tool

• Developed automation tool to analyse graphic shader ASM files and microarchitecture code using Python Scripting.

• Generated excel based reports for selected performance gain functionality: ADD3 optimization, instruction counts, redundant MOVs, JPI instruction optimization, Benchmark comparisons.

• Implemented DPI counters for checking the bottlenecks in the graphics rendering pipeline using Verilog. Academic Projects

System Verilog and UVM Design Verification of Parallel Processor System Jan 2023 – Mar 2023

• Designed 4-cores level-1 cache system by designing FSM for timing synchronization of loads n stores, MV protocol to avoid cache coherency the round robin algorithm for bus arbitration using system Verilog.

• Developed the verification plan for the implemented design and generated test cases.

• Designed the testbench architecture using environment, sequencer, monitor, interface and UVM modules.

• Deployed functional coverage and constraint randomization for increasing the verification efficiency and automated the testing using make-file and python script. C and Assembly Design for RISC-V ISA Simulator Jan 2022 – Mar 2022

• Implemented the RV32I Base Integer Instruction Set and memory using C programming and bit manipulation.

• Simulated the changes on CPI, instruction counts, register values and to compare and analyse the results on the branch predictor algorithms.

• Verified the simulator by implementing assembly-level test cases in mem files and a python script. System Verilog Design and Verification of 8237A DMA Controller Apr 2022 – Jun 2022

• Developed RTL Design for the DMA controller in the single transfer mode and simulator to interface it with CPU and memory module.

• Designed verification plan and worked on system-level and block-level verification for the priority encoder block.

• Verified the bus-functional model by issuing load/store commands using assertions, constraint randomisation and deterministic tests to verify the controller functionality. System Verilog Design for DDR4 Memory Controller Oct 2021 – Dec 2021

• Simulated a memory controller with shared last Cache of 4-cores, 3.2GHz processor employing single memory channel.

• Implemented Open Page Policy and Bank Parallelism in the System Verilog simulation.

Contact this candidate