Analog Design Full Time

Sagar Pralhad Rane

+1-602-***-**** • adzm4i@r.postjobfree.com • LinkedIn

SUMMARY

Electrical Engineering Graduate student with 4 + years of experience in the industry out of which (3 + years of experience in analog design, IO design and characterization, and ramping up the new graduates in project execution and delivery) and 1 year as a SoC Verification Engineer. Currently looking for Full-time opportunities starting May 2024. EDUCATION:

M.S. Electrical Engineering Expected Graduation – May 2024 Arizona State University, Tempe, AZ, USA GPA 4.00/4.00 (Top in Dean’s List) B.E. Electronics and Communication Engineering May 2019 KLE Technological University, Hubli, Karnataka, India ` FCD (First Class with Distinction) RELEVANT COURSEWORK:

Advanced Analog design, Mixed-Signal Integrated Circuits, Switched Capacitors (On-going), PMIC (Future Course - 2024) PROFESSIONAL EXPERIENCE:

Sankalp Semiconductors, Hubli, Karnataka, India: Analog Mixed Signal Design Engineer Sep/2020 – Aug/2022 Worked on LVCMOS IO's, GPIO's, Amplifiers from 10nm to lower nodes up to 3nm for Diodes Incorporated & Intel, USA.

• Design of LVCMOS 1.8V & LVCMOS 3.3V Non-Fail-Safe IO IP’s. Making sure the IP meets specifications across PVT.

• Design of Level Shifter, Predriver and Driver circuit for Transmitter, Schmitt trigger for Receiver platform.

• Design of Glitch filter to remove glitches from the power supply.

• Simulating and analyzing the impact of Aging, EMIR event on circuit. It includes analyzing and fixing violations.

• Simulating the GPIO circuit for post layout extractions. Making sure the IP meets specifications across PVT.

• Simulating the circuit behavior during an ESD event. It includes analyzing and fixing violations of current and voltage violations during ESD events like CDM and HBM.

Robert Bosch Engineering and Business Solutions, Bangalore, Karnataka, India: SoC Verification Sep/2019 - Sep/2020 SUMMER INTERNSHIPS: Summer/2023

Texas Instruments, Phoenix, USA: Analog Design Intern May /2023 - Aug/2023 Worked on the newest process of Texas Instruments LBC10 MV which has lesser Resistance per area when compared to older technology nodes.

Blocks worked on: Bandgaps, Diodes (45 V/120 V/LDMOS), Low Side FET Drivers, Startup Rails, Track & Hold circuits. PROJECTS:

Design of Folded Cascode Amplifier with a Class AB Output Buffer

• DC gain> 80dB, Unity Gain Bandwidth > 10Mhz, Phase margin>60 and Gain margin>15dB. Design of Telescopic Cascode Differential Amplifier

• DC gain>50dB, Unity Gain Bandwidth > 50Mhz, Phase margin>60, and Gain margin>15dB. Design of Bandgap Reference

• Designed a Bandgap voltage circuit across a temperature (-20 C to 85 C) with a variation of 10mV. Design of CMOS Beta-multiplier based constant-Gm current reference circuit of 10uA.

• DC simulations were run to study the difference in IREF2 and IREF1, variation of V_bias measured with respect to variations in VDD and variation of Gm and V_bias with respect to variation in temperature (-20 C to 85 C). UNDERGRADUATE INTERNSHIPS: Spring 2019

Analog Design Student Intern: IO circuits @Sankalp Semiconductors, Hubli, Karnataka, India

• Designed LVCMOS TX and RX 3.3V/Bidirectional IO in Cadence Virtuoso for I2C platform in 180nm technology as a part of my Undergraduate research project guided by mentors from Sankalp Semiconductors ADDITIONAL POSITIONS OF RESPOSIBILTIY: Spring & FALL 2023 Graduate Teaching Assistant Advanced Analog IC Design with Dr. Bertan Bakkaloglu & Serial Links with Dr. Hongjiang Song.

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