Bret Raymis

Yuma, AZ 928-***-**** Home 858-***-**** Mobile adzgyn@r.postjobfree.com

Skype live:bretraymis LinkedIn https://www.linkedin.com/in/bretraymis Zoom account

CAREER SUMMARY

Staff level with extensive experience in layout floor planning, standard cell planning, hierarchical layout assembly, bottom up to top down, device matching, place-and-route (P&R) of large digital and analog blocks, shielding and guard ringing, DFM, tape out GDSII format and E-beam mask generation

Broad and deep knowledge in multiple complex designs for PMIC, analog, digital, mixed-signal, high speed GHz RF, Datapath and standard cells

Enjoy being a leader of a new company or capable of doing stand-alone work or leading a back-end team

Concurrently supervised up to twenty-five (25) designers and six (6) projects

Very capable to work from home, WFH, or onsite to design layouts for entire integrated circuit, construct layout plans, create, debug and document new design flows

Deliveries made on-time with minimal area

Secret level security clearance issued Jan 14, 2021. Expired Feb 2023.

Passionate about doing the business development necessary to create companies to innovate and design solutions for complex problems for new markets

Tape out on over 50 chips with 35 years’ experience with Cadence and Mentor layout design software

Very strong analytical and problem-solving skills, with an ability to create or debug custom physical design kits flows

TECHNICAL SKILLS & TOOLS

Platforms: Unix/Linux Redhat, Netlists, Microsoft Office.

Spectrum Internet: Typical download speeds 500 Mbps. Available 1to 3 Gbps

Tools: Specialize in Cadence 6.1/12.0 Virtuoso VX, First Encounter, Innovus, Assura, PVS, Mentor Calibre, Synopsys

Technologies: IBM 5-7 nm, Samsung 10-14 nm Finfet, TSMC 65-20 nm Finfet, TSMC/GF 40-130 nm, XFAB XT018

Hardware and environment: 32-inch HP monitor, HP Spectre X360 15X laptop, private office, VPN

Media: Zoom, Google Meet, Skype or Microsoft Teams

PROFESSIONAL EXPERIENCE

Jan 16, 2023 – June 23, 2023 APEX Semiconductor, Raleigh, NC

Remote ASIC Layout Engineer III

Lead on LIN block in XFAB XT018 process

Instrumental bringing up the complex PDK flow for high voltage SOI process

Completed final dummy fill for zero density issues

Aug 8, 2022 – Oct 28 2022 Numem, San Jose, CA

Remote Physical Design Engineer

Verification of main core memory design using Synopsys Custom Complier in TSMC 22 nm

Documentation on Windows to Synopsys, density fill, DRC, LVS and LPE flows

Oct 2021 – August 2022 Geologics Corp., Alexandria, VA

Remote Layout Engineer for Raytheon, El Segundo, CA

Assigned to design 40 GHz ADC, DAC and SERDES in GlobalFoundries SOI 45 nm

Layout and schematics on core cell for regulator with bipolar devices.

Sept 2020 – Sept 2021 Softworld Inc, Waltham, MA

Remote Layout Engineer for Draper Labs, Cambridge, MA

Assigned to design a mux & sensor block in GlobalFoundries 12LP in 6 weeks while mentoring a junior engineer

Lead layout engineer in Intel 22ffl process for secret project creating vref, high performance amps, bandgaps, sensors. muxes, and switch blocks

July 2019 – Nov 2019 Manpower Group, Milwaukee, WI

Design Aid/Senior Layout Contractor for IBM, Yorktown, NY

Remotely supported the Zurich, Switzerland group doing bottom to top level memory arrays on AI project

Samsung 14 nm Finfet with 20 levels of metal

April 2019 – May 2019 Covalar Design, Richardson, TX

Senior Layout Contractor for L3T, Plano, TX

Only a 5-week contract for night vision circuits in TowerJazz 13 nm

Assigned the ADC very complex 12-micron wide column decoder with mirrored logic without matching schematics

Sept 2018 – Dec 2018 Triple Crown, Austin, TX

Senior Layout Contractor for Lockheed Martin, Moorestown, NJ

Lead designer on 18GHz RF LNA analog circuits in SIGE 90nm, 10-metal Global Foundries process

Laid out a 4-stage amplifier

Extraction of the amplifier compared excellent to circuit simulations on first pass

April 2018 – Sept 2018 CTG, Buffalo, NY

Senior Layout Contractor for IBM, Armonk, NY

Remote layout on macro devices below 7nm in joint technology by Samsung, Global Foundries and IBM

Communicated with seven (7) different engineers on twelve (12) different layout designs from around the United States

Feb 2018 – April 2018 W3Global, Coppell, TX

Senior Layout Contractor for Micron Technology, Minneapolis, MN

Layout on GHz ASIC delay logic in TSMC 28nm process

Aug 2017 – Sept 2017 Imperial Staffing, Austin, TX

Senior Layout Contractor for ARM, Deerfield Beach, FL

Layout of Bluetooth bias LDO block in TSMC 40/45nm process

May 2017 – Aug 2017 Technical Links, Henderson, NV

Lead layout Designer for Ambiq Micro, Austin, TX

Lead designer an ultra-low power RF 40/45nm ultra-low power TSMC process

Dec 2016 – March 2017 Synapse Design, Santa Clara, CA

Senior Layout Contractor for Skyworks, Woburn, MA

Responsible for entire analog and digital portion of chip in IBM/Global Foundries SOI process

Porting and shrinking analog switches, voltage regulators and LDOs from IBM to TSMC SOI 11nm process

Aug 2016 – Sept 2016 Synapse Design, Santa Clara, CA

Senior Layout Contractor for Intel, Chandler, AZ

Laid out connections on a top-level analog block in TSMC 28nm for a 5G RF chip

Worked closely with chip lead designer in verifications of DRC, LVS, VMSLAY and interpreting the results

May 2016 – July 2016 Qualstaff, San Diego, CA

Senior Layout Contractor for Peregrine Semiconductors

Lead person for LNA RF chips

Floor planned and instructed other personnel on layout

Feb 2016 – April 2016 netPolarity, San Jose, CA

Layout Contractor for Rambus

Completed a very complex high-speed 30GHz transceiver block in Samsung 14nm in just 3 months

May 2011 – Nov 2015 Qualcomm, San Diego, CA

Senior Mask Layout Designer

Lead for DDR 2.0 and 2.5 blocks currently in Snapdragon 810 processor

Completed the layout of analog LDO and op amps blocks for SerDes

Main physical designer driving place-and-route Cadence First Encounter for ten (10) DDR control blocks

Lead designer on PMIC for James Doyle creating large power transistors and top-level plan.

Led an international team on a bandgap and PLL transceiver using Samsung 10nm FinFET for Snapdragon 835

EDUCATION & OTHER TRAINING

Attended Montgomery Community College for one year, Montgomeryville, PA

US Army Avionics technician with 101st Airborne Division, Medevac unit at Fort Campbell, KY

PAST ACTIVITIES

Elks club member at Yuma lodge #476

CEO and Chairman for PWRJOULE 2018-present

Board of Directors for “I Love a Clean San Diego,” 2012 - 2014

Board of Directors for Palm Schwenkfelder Church, Palm, PA

Founder and President for Big Country Neighborhood Association

Contact this candidate