SUBJECT

A highly motivated Digital Electronics Background Engineer, Interested in Application position in Digital ASIC/ FPGA based systems or Research and Development with Testing and Verification engineering process.

SKILLS

Ability to quickly pick up new concepts and contribute with innovative solutions

Strong Digital Logic Design background with ability to do RTL Design in VHDL and Verilog

Verilog, VHDL synthesis System Modeling and Simulation testing technology.

Testbench implementation to verify Asic Design functionality errors.

DFT (Design for Testability) and Test Asic block-level to top chip-level design

Ability to debug and problem solving highly technical issues

Synopsys DC-Compiler, Cadence NC-Verilog, Mentor Graphic, Tetramax for ATPG

Demonstrate self-motivation, with little supervision required

Design and deliver production quality FPGA releases from initial proof of concept up to production

Work cooperatively with systems, hardware, software engineers, and program management to ensure product success

Demonstrate the ability to architect FPGA-based systems to determine parts, interfaces, and Concept of Operations (CONOPS)

Translate system level requirements into FPGA requirements

Design and code in VHDL for reliability and maintainability

Verify designs utilizing self-checking techniques with directed and constrained random tests, while tracking functional and code coverage

Create complete documentation including requirements, verification plan, and user's guides

Support internal and external technical reviews

Hands-on knowledge of designing for FPGA implementations for hardware testing

FPGA Technology with Modelsim/Questa, Altera Maxplus, Xilinx, Aptix System

Assembly, C/C++, Visual Studio, SPICE, Unix, Microsoft Office Tools for presentations and Documentations

Extensive module design experience including thorough design and test documentation, completion and review of schematic and layout, creating and reviewing routing instructions, and design debug.

Ability to effectively analyze situations and recommend improvements.

Ability to work effectively under pressure to meet tight deadlines.

Experience completing multiple module designs including ones of moderate complexity is desired.

Has led module debug and integration of a module into system.

Understands and has performed worst case analysis.

Clear written and verbal communication skills, and ability to have technical discussions with customers

Work History

10/2016 – 03/2018 Digital Engineer - Universal Electronics, Santa Ana CA

Took ownership of digital hardware product for Engineering and fully supported it in Manufacturing by writing and implementing ECO's that fixed or improved problems.

Design Analysis, Review, Performed Debug circuit analysis of complex systems, sub-systems, under test to configure necessary system resources for test system development.

Provided technical expertise, quality testing, benchmark studies, backend research and troubleshooting of complex problems.

Support and Execute product validation and Debug activities working with Product, Quality and Test engineering production ramp -up

Analyzed faulty Digital Board and faulty performance, selected its replacement and performed final qualification for its release.

Debug firmware and software by testing units, isolating problems, and fixing bugs

Integration and Prototyping and help writing document transfer to production

Provide training and customer support on delivered system. Performed test systems, test program sets installation, and acceptance on site and at customer sites.

09/2013 – 11/2016 R&D Application Engineer Staff Members - Masimo Corps, Irvine, CA

Responsible for cross-functional team support and external supplier interface.

Performed individual tasks while functioning as a member of a team

Follow product design flow and actively seek areas of improvement to enhance ways of testing

Follow product design validation and debug activities working with Product, Quality and Test engineering for production ram up.

Analyzed faulty Digital Board, Fpga Designs performance, selected its replacement and performed final qualification for its release.

Created internal and external documentation on projects.

Update design compliance documentation with new and changing regulations;

Prepare Declaration of Conformity for all relevant products;

Collaborate with engineers of technical reports, design specialization, user documentation and improvement.

12/2006 – 09/2013 Asic Design Test Engineer - Emulex Systems Inc, Costa Mesa, CA

Perform digital design work across all aspect of the design flow from RTL to GDS

Verilog RTL coding design review and evaluation and analysis using Synopsys tools.

Perform implementation coding, block level verification and work with Verification team to validate the design

Develop synthesis constraints and perform logic synthesis

Run synthesis, CDC checking, equivalence checking and Simulation Verification

Implementation and Integration of IP Cores to SoC design

Performing logic synthesis, DFT insertion, timing analysis and timing closure

Performing thorough verification planning and execute firmware based verification

Performing block level functional Simulation verification using Testbench analysis

Generate comprehensive random and directed test cases to deliver functionally correct designs.

Validation and Execute test plans from scratch for IP’s based on specification before Integration

Executed ATPG, created test vectors for ASIC fault coverage.

Developing high coverage, cost-effective DFT methods

Drive performance verification on all DFT structures

ARM Core functionality debugging, testing, and test vector generation for production.

Verification and Implementation and Integration of various IP’s Core Technology to sub-system design block

Debug and Diagnose and Verification for functionality correctness from block-level to chip-level system integrations.

Post silicon support to ensure successful bringup and functionality assurance testing

06/2004 – 12/2006 Digital Test Design Engineer - Hughes Space and Communication Systems, El Segundo CA

Actively involving in Design for test for Spaceway ASIC/Fpga Aerospace system project.

Wrote new modules and edited existing modules in VHDL

Asic Design Verification with gate level simulation

Implement and Verification of Memory BIST logic generation

Inserted internal scan, executed ATPG, created test vectors for ASIC fault coverage.

Scan/Jtag/boundary Scan Insertion and Implement from Asic block to top-level design

Developed test scripts and utilized these scripts to quickly test multiple units from block-level to top-level design

Test coverage and test cost reduction analysis

Generate comprehensive random and directed test cases to deliver functionally correct designs.

Responsible for automatic test-bench and test-fixtures generation for all test engineering.

Debug and Diagnose and Identify all malfunctioning systems, board-level testing equipment, electronics parts, via using Simulation techniques and Testing functionalities of test failure from test group.

06/2000 – 07/2004 R&D Asic Test Engineer - LG Info comm Inc, San Diego, CA

•Perform digital Asic design work across all aspect of CDMA chipset Asic development from RTL to GDS

•Testbench design and verification of all CDMA Asic design block levels functionality

•Aptix Xilinx fpga design for testing CDMA Asic Block design on hardware board-level

•Perform testbench implement CDMA cell phone chipset both at design and hardware level

•Debug and Diagnose and Identify all malfunctioning systems, board-level testing equipment, electronics parts, via using Simulation technique and Testing functionalitiess of test failure from test group.

06/1997 - 06/2000 Associated Engineer - Currency System Inc, Irvine TX

Perform Hardware board-level design and implementation on “Currency Node” UPS System Machine.

Orcad Schematic implementation of system board-level design before PCB manufacturing. BOM generation.

Develop Altegra FPGA testing all system board circuitry at Digital and Analog circuitry level.

Responsible for all Hardware board-level testing and functionality with many different configurations testing of Electronic “Currency Nodes” sorting and inspection circuitry of UPS machine.

Successfully built Fpga VME-board to interface with UPS machine to detect blocked 'Nodes'.

Rebuilt and test Digital and Analog board for system integration new project of Space Reduction System.

EDUCATIONS

CAL POLYTECHNICS OF POMONA UNIVERSITY

Bachelor Degree in Electrical and Computer Engineering, June 1997

LEE SAUNDERS Associated, LOS ANGELES CA

VHDL Electronic Design system Application Engineering Training, June 2002

SYNOPSYS INC, MOUNTAIN VIEW CA

Design for Test Application Engineering Training. Aug 2, 2000

REFERENCES

Upon requested

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