ZILAN TONG Mountain View, CA 410-***-**** adzf3m@r.postjobfree.com Linkedin

MIXED SIGNAL LAYOUT ENGINEER

Strong knowledge of transistor, schematic, logic & complex logic fundamentals.

Resistance/Capacitance/Inductance and the associated R/C/L used to reduce IR Drop, EM and antenna issues.

Applying device matching /noise reduction techniques in Analog Circuit Layout

Analog circuit devices techniques: device matching, cross coupling, wire shielding and dummy placement, P/G rail separation, guard rings and noise reduction techniques.

Final project included a BICMOS mixed-signal Transceiver Circuit (approx. 10k devices) CORE SKILLS

Soft Skills:

● High sense of teamwork and collaboration

● Excellent interpersonal skills & effective leadership skills

● Positive attitude and strong work ethic with a passion for quality work

● Strong organization and effective time management Layout Cadence Tools:

● Virtuoso Layout Editor (VLE), Virtuoso XL Editor (VXL).

● Virtuoso Schematic Composer. PCELL utility.

● Assura DRC/LVS/Soft-Check and Dracula DRC/LVS.

● Chip Assembly Router (CCAR, a routing tool)

Platforms & Applications: Windows, MacOS, Linux, MS Word, Excel, PowerPoint, VI(m) Editor. PROFESSIONAL OVERVIEW

PSIQUANTUM – Palo Alto, CA JULY 2022 – MAY 2023

ASSOCIATE LAYOUT ENGINEER

● Collaborated with cross-functional teams regularly to develop and implement custom 22 nm IC layout designs.

● Utilized Cadence Virtuoso, tools to perform layout design, verification, and debugging while ensuring DRC and LVS compliance.

● Created and maintained layout documentation, including design specifications and reports.

● Demonstrated expertise in designing and implementing analog and digital circuits. Projects:

● Designed Ring oscillator layout for a low-power CMOS circuit with a frequency of 500 MH.

● Created and modified layouts in Virtuoso XL with Pegasus DRC & LVS on GF 22FDX-PLUS process.

● DACs, backside RDL pads & routing with TSVs (added decoupling caps as space allowed, then added to schematic).

● Ran fill script and added manual fill as required TESLA INC. – Fremont, CA SEP. 2020 – JULY 2022

PROJECT ROADRUNNER-PROCESS TECHNICIAN

● Held a position in the R&D facility which focused on continuous research surrounding work with the actual build of their next generation 4680 battery cells. Direct role included rolling materials into batteries and welded before processing to assembly.

EDUCATION & CREDENTIALS

Analog and Mixed-Signal Layout Design (2022), SILICON DRAFTING INSTITUTE - SAN JOSE, CA. Bachelor of Science-International Relationships (2019), NEVSEHIR HACI BEKTAS-I VELI UNIVERSITY - NEVSEHIR, TURKEY Completed Layout Projects & Blocks:

● Designed various circuit blocks with 0.1 um 5-layer metal BISMOS well technology

● All basic & complex logics, Data Latch, D Flip-Flop, Shift Register, SRAM, Bias, PLL

● Clock generator, ESD’s, I/O Devices, Bond pads and Scribe line. LANGUAGES

English: Fluent Kurdish: Native Turkish: Native Spanish: Basic

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