Andy Khuu

*** ** ***** ***** *.E Phone: 206-***-****

Renton, WA. 98059 Email: adyyt2@r.postjobfree.com

OBJECTIVE: Looking to obtain a job as an experienced IC Circuit of Electrical Engineer position to modify existing layouts and utilize my knowledge in the IC design by performing layout cells in analog, digital, mix signal and top level layout.

SKILLS PROFILE

Over seven years of experience in working with Cadence layout toolset

Familiar in working with Unix, Cadence Virtuoso XL, Diva (DRC/LVS/ERC), (DRC/LVS) and Hercules Avant (DRC/LVS/ERC/ANT), and Assura verification tools

Know how to modify existing layouts, DRC, LVS, and arrange layout cells

Experience with design digital standard cells, analog layout, guard ring and full chip

EMPLOYMENT HISTORY

Aviation Maintenance Technician, Allflight Corporation, Kent, WA 07/05/2022-current

Assist lead technicians with cleaning, prepping, inspecting, testing and repairing aircraft windows, components and equipment.

Production Assembler, Hy Security, Kent, WA 02/28/2022-06/21/2022

Assemble electric box, panels of gate security system with batteries, transformer, chassis, wire harness routing.

Test Technician, Sanmina, Bothell, WA 03/15/2021-11/04/2021

Perform defect finding on circuit boards, repair and replace electro-mechanical components

Read schematics, diagrams from eMatrix. Measure resistors, capacitors, impedance. Check for voltage short and open components on circuit boards.

Perform functional imaging testing of a finished medical ultrasound device.

Perform resilient self-test, calibration for channel board and transducer select board on space station.

Record each component replaced in Elog for company and Rep Track for customers.

Mechanical Assembler, Fluke, Everett, WA 09/28/2020-02/17/2021

Visual inspect, assemble face masks

Measure, cut pipes and boards; assemble shelves under worktables.

Assemble magnetic sliding tool kits and chain with keys for alignment sensors, solder batteries wires to PCB boards for rotalign sensor and solder batteries wires through holes for optalign sensor. Wrap electrical wires under batteries with insulation tapes around batteries.

· Assemble some packages for laser light: rotalign and optalign.

· Labels and packages for Thermometers, Digital Multimeters and Clamp Meters

Test RH percentage of Relative Humidity and Temperature Meters at 75 percent RH with salt and distilled water. Report pass/fail data.

Mechanical Assembler, Aim Aerospace, Auburn, Washington 11/20/2017-07/02/2020

Install sleeve and insulation for aircraft ducting

Prepare panels, cleaning with alcohol, read documents

Prepare bonding mixture

Perform etching process for panels with bonding mixture

Inspect panels and fix minor etching details

Mechanical Assembler, BTG, Bothell, Washington 11/21/2012-8/13/2015

Work in clean room

Solder elements to core wires under microscope

Assemble core wires with elements that can go into blood veins

IC Layout Engineer, TriQuint, High Point, North Carolina 5/2012-5/2012

Worked with layout of 3 metal layers of VLSI RF layouts for updated diode, clamp, and esd pads in IBM_PDK Runset

Modified existing layout and debug problem in the LVS data report for substrate floating

Layout tools: Cadence Virtourso and IBM_PDK with DRC and LVS

Mechanical Assembler, Eldec,Corporation, Lynwood, Washington 11/2011-03/2012

Calibrate test machine

Assemble inductors coils

Tint wires

Solder wires between inductor coils under microscope

Calibrate inductors within specified frequency range

Tint conductors

Wrap inductor wires to conductor wires

Touch up solder.

Analog Layout/Mask Engineer, Impinj, Seattle, Washington 11/2010-12/2010

Modified existing layouts of a VLSI RFIC memory in 45nm techngoloy.

Design layouts for controlling circuit section that in charge of memory tags: aeon_bias and aeon_bias vittoz.

Worked with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC Assura verification

Analog Layout/Mask Engineer, Zarlink, San Diego, California 07/2009-10/2009

Worked with floor planning and VLSI layouts of a hearing aid in 18nm tsmc RF technology

Design layouts of 4 esd-pads and 1M-ohm resistor

Design layouts for an oscillator and charge pump in CM018MMRF technology

Design connection of m3 between the hybrid layout and decoder’s layout

Design layouts for switches and caps for a decimator

Worked with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC Assura verification

Mechanical Assembler, Carlye Inc, Tukwilla, Washington 01/2006-07/2007

Work in a team

Strip wires

Crimp pins

Heat shrink

Assemble cables

Analog Layout/Mask Engineer, Semtech, Mira Mesa, California 10/2005-10/2005

Worked with floor planning of a VLSI array

Modified existing layouts and fixed DRC errors from a gds file: dac16 layout in Bipolar and 35nm polar technology

Modified existing layout for schematics with bipolar transistors and analog devices, pcomp and pcomp0

Modified existing layouts for three stages of a comparator: plogic, plogicd and plogico

Modified existing layout for a schematic, imirror9 with npn and pnp

Work with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!

Physical Design Engineer, Intel, Hillsboro, Oregon 11/2003-12/2003

Design VLSI layouts of logic control in 80 nanometer CMOS technology

Work with digital layout block. Design layouts for nvstctl_jtagtop with padin and padout. Draw layouts for nvstctl_jtagselaccess5, nvstctl_jtagmux4, jtagselaccess5, nvstctl_jtagtrxmux, nvstctl_jtagdomux, txrmux, tdmux, nvstctl_jtagtdomux, nvstctl_seldecoder, decap, pad in/pad out, buffers and nvst_ctl_jtagtop control block

Modified exixting high-speed layouts of phase locked loop, logic divider, flip-flop and charge pumps for a high-speed and low power addressable

Work with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!

Physical Design Engineer, Intel, Hillsboro, Oregon 10/2002-1/2003

Design layouts for VLSI p861 chipset project

Work with pipeline architectures, rows and columns for a chipset. Design data path in patterns that feed data from right to left and from top to bottom for multiple rows/column

Design I/O connections in different layout structures

Modified existing high-speed layouts for dataspinebufblk, basebufblk, globalbufblk, compfiller, leftspinebufblk, leftsplinevss and clkgen

Fixed shorts and overlaps in layouts with power template. Fix lvs errors in layouts of front-side buses

Design decaps for VDD pad and VSS pad to reduce power noise

Design layout for high voltage decaps layout with VCCDDR and VSS

Troubleshoot LVS errors

Align metals, m6, m4, m5 and m3 to reduce inductances in layout of top_comp.

Worked in ddr_anaprdrvr layout to connect between multiple power rails and pad

Connected vcca to vcc, vssa to vss, vccddr to vccddr, and esd to pad in a top level layout

Fix text labels in top-level layout and input pads

Perform all verification flows

Work with layout tools: Cadence Virtourso/Virtourso XL and DRC/LVS/ANT/ERC verification with Hercules Avant!

Analog Layout Engineer, CMOS Micro Device, Campbell, California 3/2002-3/2002

Design layouts for memory chip project

Worked with layouts of phase locked loop (PLL), logic divider, Op-amps, flip-flop with bi-directional transistors, and charge pumps in 18nm TSMC technology

Work with layout tools: Cadence Virtuorso/Virtourso XL, DRC/ERC with Diva, and LVS with Dracula

Analog Layout Engineer, NSC, Santa Clara, California 10/2001-2/2002

Worked with floor planning of existing VLSI layouts for audio chips

Modified existing layouts of op-amps, resistor chains, volume controller, selectors for lm4841 chip project

Design layouts for capacitors with common centroid among them

Work with floor planning and single/double guard rings in cs65sg high voltage technology

Fixed LVS errors for lm4842chip

Modified existing layouts for lm4901 chip in cs7_5v technology

Modified layouts for lm4890 project

Design pad ring to cover substrate area for lm4894 layout chip

Work with layout tools: Virtuoso-XL with P-cells and DRC and LVS with Diva for small audio chips

Analog Layout Engineer, IC Media, Mesa, Arizona 1/2001-7/2001

Design layouts for project 108t

Worked with pad rings for VLSI project 532 layout and I/O connections for 105_V2

Fixed layout errors of an ESD layout pad with a tri-state buffer

Tested a DRC deck in 0.25micron UMC technology.

Worked with data paths and arrays for project 108t CMOS Imager PC Camera

Worked with layouts of ramp generator, ADC, voltage generators and PLL8001

Design layouts for row decoder, column decoder, clock control logic, comparator

Worked with floor planning of a 1290x1034 CMOS imager

Design data paths of 1290x1034 CMOS pixels imager with 4.5um pitch with 45nm UMC technologies

Assigned pin locations in layout for analog/digital, and provided a double power source for the imager

Work with layout tool Cadence Virtuoso; DRC/LVS/ERC/ANT with Diva and Hercules

Analog Layout Engineer, Global Span, Princeton, New Jersey 7/2000-7/2000

Worked with inputs of interconnection of transistors in array

Applied matching technique for transistor

Work with layout tools: Cadence Virtuoso

Compiler/Verification Engineer, Virrage Logic, Bellevue, Washington 1/2000-2/2000

Draw VLSI layouts for I/O of dual CMOS RAM memory

Verified the dual CMOS RAM architecture and documents

Work with layout tools: Cadence Virtuoso

Technical Co-Op student, JPL, Pasadena, California 3/1998-10/1999

Design rule check and fix width and length of layout transistors.

Design rule check and work with spacing between metals and poly layers

Verify layouts of a twelve bits Sigma-Delta ADC of a video camera.

Design schematics for a 12 bit adder and Op-Amp at high gain

Modified existing ADC layout from MOSIS technology to Lockheed Martin technology

Record test chips

Work with layout tools like L-Edit and Cadence

Technical Co-Op student, JPL, Pasadena, California 6/1997-12/1997

Draw I/O connection for data path between four special purpose chips

Build test boards on breadboard

Work with Labview to assist an engineer in a moving robot.

Assisted other technical staff in circuit simulation

Design layout of a VLSI 4:1 split array transistors

Recorded data of some simple test chips from oscilloscope

Work with software tools: OrCAD and MicroSim

EDUCATION

Bachelor of Science in Electrical Engineering 1998

University of Washington, Seattle, WA

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