Machine Learning C#
Resume:
Sai Venkata Pavan Santosh Kumar Kottamasu
904-***-**** ********@***.*** www.linkedin.com/in/skottama EDUCATION
Master of Science in Electrical Engineering Arizona State University, Tempe, AZ 3.70 GPA May 2023 Bachelor of Technology in Electronics ANITS, Visakhapatnam, India 7.66 GPA Apr 2018
& Communication Engineering
TECHNICAL SKILLS
Design Automation Tools: Cadence (Virtuoso, Spectre, Hspice), WaveViewer, MATLAB, Design Compiler, Silvaco and LabVIEW, ADE XL, ADE L.
Programming Languages: System Verilog, VHDL, TCL scripting, perl, Python, MATLAB, C# Frameworks. Relevant Coursework: Analog Integrated Circuits, Digital Systems and Circuits, Statistical Machine Learning, VLSI Design, Nano Fabrication and Characterization, Constructionist Approach to Microprocessor Design, Advanced Analog Integrated Circuits, Computer Architecture, Advanced Silicon Processing, Semiconductor Characterization. WORK EXPERIENCE
System Validation Engineer - Graduate Technical Intern, Intel Corporation, Remote, USA May 2022-Dec 2022
● Collaborated with the iVe-XPV team situated at Santa-Clara, worked on the XEON product validation, validating software and hardware configs.
● Create logs for the test-line failures and process them for reruns in upgraded silicon.
● Developed architecture Validation and created new configurations using new BIOS. Worked on Intel Automation Verification tools.
Senior Systems Engineer, Infosys Ltd, Bengaluru, India Jun 2018-Jul 2021
● Developed websites and databases which keeps track of Financial Data of customers using C# frameworks and SQL.
● Collaborated as a support programmer which involved in clearing bugs and glitches in the applications using various debugging mechanisms.
ACADEMIC PROJECTS
ASIC Acceleration for Graph Convolution Neural Networks Spring 2022
● Coding the GCN using System Verilog, verified the functionality and synthesized the design using Design Compiler.
● Performed APR (Automatic Place and Route) using Innovus, performed post-APR, exported the GDS into layout and performed DRC and LVS check for final layout verification. Calculation of power using Innovus. Design of a 16x16-bit Register file (RF) using finFETs Spring 2022
● Designed a 16x16 RF array using 8T SRAM cell with synchronous, dynamic read and write operations using 4x16 decoder. Performed extraction on the DRC/LVS of the layout and verified the functionality of the post layout extracted simulation.
● Reported the fast and slow corner cases for the RF register file, and the maximum operating frequency based on the post layout extracted simulation. Optimized the design for better performance. Design of single ended NMOS input folded cascode amplifier with class AB buffer Amplifier Fall 2022
● Designed a single ended NMOS input folded cascode with power dissipation < 2mW. A DC open loop gain> 90dB and phase margin> 60 degrees to ensure stability and slew rate of 10V/usec. Gain margin is around 15dB and higher.
● This involves the design of bias circuit, beta multiplier and class AB amplifier. Verification of design can be confirmed by matching the symmetric transistors in both beta multiplier and AB amplifier. CMRR and PSRR of 80dB are compiled.
● AC, DC, Transient and Noise analysis are performed for testing the overall circuit and 3rd harmonic distortion is studied. Design, Simulations, and analysis of a Low-Dropout Regulator Fall 2021
● Designed a Low-Dropout regulator using Cadence (CMOS TSMC 0.25um Process) with voltage gain > 40dB, power < 0.5mW, regulated voltage of 2.3 V, and bandwidth of 1MHz. Plotted the frequency response and calculated the 3dB frequency.
● Implemented by designing a Transconductance amplifier and a driver stage for the required amount of current at the output. Performed AC and DC analysis in open and closed loop configurations and performed transient line regulation.
Implementation of LRUIPV Cache Replacement Policy in gem5 Fall 2022
● Implementation of Pseudo Least Recently used Cache replacement algorithm in gem5 using the best insertion promotion vector. Implemented the Policy in gem5 using C++ programming language. SVM and SVM Ensembles in Breast Cancer Prediction Fall 2021
● Predicting Breast Cancer disease using machine learning algorithm techniques like Support Vector Machines and Ensembles SVM using Python. This involves selecting good feature selection for processing data with high accuracy.
● The Algorithm involves selecting a good Feature selection for pre-processing data and training the processed data to kernels, comparing various accuracies with various kernels.
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