Anil S N

: adydjr@r.postjobfree.com :91-973*******

Professional Summary:

* ***** ** ********** ** Custom Layout Design on 180,150,130,110,40,28,10nm & BICS (3D NAND)technologies.

Good knowledge of CMOS concepts and analog mixed signal layout techniques.

Excellent record for Quality of work and on time delivery. Won many awards for excellent performance.

Worked with TSMC, GF, Magna, Samsung ST and KIOXIA microelectronics foundries.

Work Experience:

Presently working as Staff Mask Design Engineer in Western Digital since Aug 2022.

Senior Layout Engineer in Cyient Ltd from June 2015-AUG 2022. Educational Qualification:

B.E in Electronics and communication from Visvesvaraya Technological Universty, Karnataka.2014.

Advanced PG Diploma in VLSI ASIC Design from RV-VLSI Bengaluru.2015. EDA Tools and Expertise:

Custom Layout design using Cadence Virtuoso and Virtuoso-XL, Mentor Pyxis.

Layout Verification (DRC, LVS) using Calibre,PVS.

Chip level DRC & LVS and over-all responsibility of Blocks

Experience in fixing IR issues.

Hands on experience in handling different EDA tools. PROJECTS.

Western Digital(SANDISK).

Technology TSMC 28nm & BICS 9.

Layout Tools Cadence virtuoso xl, Mentor graphics Calibre Description Worked on R&D project related to MRAM was responsible for Analog modules such as Sense amplifier Current mirrors, Power bus.

Worked in BICS 9 technology, was responsible for VGBST Pump and integration at module level. ANSEM (An CYIENT company).

Technology GF 40nm, TSMC 28nm.

Layout Tools Cadence virtuoso xl, Mentor graphics Calibre Description Worked on three projects, two with GF 40nm, and other one with TSMC 28nm.Worked on Low voltage bias, dldo,ldo,oscillator, in GF 40nm.Currently working on Sense module for SRAM in TSMC 28nm.

Qualcomm ODC.

Technology TSMC 150nm, GF 130nm SOI, Samsung 10nm. Tools Cadence Virtuoso XL, Mentor Graphics Calibre. Description Worked on mainly LNA and PMIC projects at Qualcomm ODC, Responsibilities includes working as individual contributor and Team.

Under LNA projects which was on GF130nm SOI process, worked blocks such as post attenuation switch, LNA core, Glue logic, Various Tuning Circuits, Current Bias, RF routing cell. Integration at Chip Top level and Module level.

Under PMIC projects which was on TSMC 150nm process, worked on blocks such as Current sense, Error Amplifier, LDO, Duty Modulator, Level Shifter, Charge Pump, Oscillator, Class AB amplifiers. Integration at top level and Module level.

Worked for sub blocks of PLL which was on Samsung 10nm finfet, Did OTAN, Capacitor Bank, Current reference blocks.

CONTINENTAL ODC .

Technology GF 130nm.

Layout Tools Cadence Virtuoso XL, Cadence PVS.

Description Worked on Bump Current Module, this module delivers 3 different currents 10ma, 32ua, 256ua, did sub blocks such as OTAN, OTAP, CAL blocks, took care of integration at sub module level and at the module level. Lead two junior engineers.

BOSCH ODC

Technology ST microelectronics BCD 110nm

Layout Tools Cadence virtuoso xl, Mentor graphics Calibre Description Worked on three projects at Bosch odc, worked on boost module, Relay driver,Relay controller, Output Stage, wake up stage, Charge Pump, CAN,Current generation and Level shifter module. Worked on Power planning for one of the chip, Worked till Chip top, was the point of contact from odc to client for one project. Used Bosch own tool to clean up IR issue, Handheld the chip till Tape out is done successfully.

AUDIENCE (Knowles company) .

Technology Magna 180nm.

Layout Tools Mentor graphics PYXIS, Mentor graphics Calibre Description Worked on two different projects, Did Oscillator, Class AB amplifier, LDO, CP mems blocks. Personal Details.

Date of Birth : 12-Oct-1992.

Sex : Male

Languages Known : English,Kannada and Hindi.

Nationality : Indian.

Martial Status :Married

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