Jithendra Pulivarthi

Chicago, IL Illinois • +1-312-***-**** • adxg4i@r.postjobfree.com •linkedin.com/in/jithendra-pulivarthi-216835248/ •https://bit.ly/3vJdeqp Peers and Honours

Board Treasurer ETA Kappa Nu (HKN) Kappa Delta Chapter • Gold Medal (Top 50 University Admission • Silver Medal Research Day SRM University, AP 2022, 2021 • Gold Medal Winner of Tech Fest, at Sir C.R Reddy College of Engineering • (Hayakawa) Japanese Language Level – N5 certified • Gold Medal (Top 50 University Admission). World Wide Fund (WWF) Best Fund Raiser of 2022 Student Chapter with an 18000 Rupees for Saving Animals and Nature life.

Education

Illinois Institute of Technology, Chicago, IL Graduation: May 2024 Master’s in Electrical and Computer Engineering

Specialization: VLSI and Microelectronics – Adv VLSI Design, CAD- VLSI Design, Dig-SoC-Design, High performance VLSI-IC, Semiconductors, Special Prob/Project. SRM University, Andhra Pradesh Graduated: May 2022 Bachelor’s in Electronics and Communication Engineering Specialization: VLSI, Digital and Analog Electronics, Digital Signal Processing, VHDL using FPGA, ML, Embedded Systems, Quantum Electronics, Microprocessors Skills

Coding and Conceptual: Python, C, Perl, VHDL, TCL/TK, Verilog, System Verilog, H-Spice •Technologies: (specializing in Microsoft Office and Google programs), Cadence, Model Sim, Synopsis, Xilinx(VIVADO), EDA tools •Interpersonal: Research, Motivational, Organizational, Volunteer. Industrial Work Experiences

Graduate Student Researcher ECE - IIT Jan 2023

VLSI Design and Automation Lab (DA LAB) IIT-Chicago, IL

• working on Low power SRAM cells for power optimization using FinFET and Planar Based Technology Nodes. optimizing leakage power at the system and circuit levels using CAD tools . Utilized Tools and Technologies are Verilog, System Verilog, H-Spice, Synopsis, Model Sim, VHDL, C/C++, Tcl-Tk, Python, and RTL Design.

VLSI Design Junior RTL Design Engineer June2021 – Aug 2021 VLSIUVM TECHNOLOGIES (OPC) PRIVATE LIMITED Nagpur, India

• I was contributing to the Verilog code generator project by creating synthesizable RTL designs code, developing test plans, and performing simulation checks, and timing checking. By utilized The EDA tools, Model sim Altera, Xilinx. VLSI Student Intern Jan 2021 – Mar 2021

Electronics Corporation of India Limited (ECIL) Hyderabad, India

• During this internship, I adopted the ideas of Verilog code generation with concepts of digital electronics, and the implementation of an 8-bit ALU utilising the Verilog language. The functional verification of design testbench is employed, and all functional operations are checked using the tools Xilinx (ISE). Telemetry Microelectronics Student Intern Dec 2019 – Jan 2020 Defence Research & Development Laboratory (DRDL) Hyderabad, India

• Understanding the technology used in missiles and the Telemetry concepts on which the basics of microwave applications. Projects

Performance Evaluation of 6T and 8T SRAM cell using ASAP7 Technology IIT-Chicago, IL

• In this project 6T and 8T SRAM is designed in ASAP7 and parameters analysed using SPICE, Cscope. Also compared the layout vs schematic (DRC, LVS, PEX) synthesis • Tools / Technologies: ASPA7(7nm), Cadence, SPICE. Low Power Optimization Techniques from System Level to Circuit Level IIT-Chicago, IL

• In this project, I started working on power optimization techniques using system-level to circuit-level analysis. I used the clock gating, loop unrolling method and clock gating techniques using C and RTL Verilog code, and I also understood the ultra-low power optimization using cache modification. When performing functional verification with independent tools such as Modelsim Altera and Cadance Virtuoso. I am continuing my research in ultra-low power RTL level. CAD tools design for STA by using Tcl/Tk and C programming (CAD) IIT-Chicago, IL

• Developed graphic interface for STA and took user’s IP using TCL/TK • Developed C program to do slack time analysis which was invoked from Tcl/Tk, and final output was printed on GUI.

Design of a Unified XOR Ring Oscillator PUF-TRNG Circuit in 45nm CMOS Technology SRM University, AP

• Various architectures and designs have been explored in earlier research work, thus in this current study we investigate the XOR function form of unified XOR-RO-PUF TRNG circuit, the calibration and parameters analysis are taken while comparing with prior RO-PUF-TRNG papers. • Tools / Technologies: Cadence (VM ware), CMOS, FPGA • Presented in Research Day 2022 SRM University, AP • Published in IEEE. Performance Evaluation of 6T SRAM cell using 90 nm Technology SRM University, AP

• In this project performance evaluation of 6tsram cell topology and analysing the different parameters using 90nm node. • Tools / Technologies: Cadence

(VM ware), CMOS • Presented in Research Day 2021 SRM University, AP • Published in IJERT. Implementation of the Communication Protocol SPI by the HDL-Verilog Language. SRM University, AP

• In this project design and development of SPI by create the single input Master and single input Slave. For Finding the Full duplex Communication• Tools / Technologies: : EDA tools, Model sim Altera, XILINX(VIVADO)• Presented in Research Day 2020 SRM University, AP • Submitted in IEEE. Image Enhancement Based on Hardware Descriptive Language. SRM University, AP

• The project deals with image enhancement techniques. The main theme is the enhancement of image to find A) Threshold Operation B) Invert Operation C) Brightness •Tools / Technologies: MATLAB, XILINX(VIVADO)•Presented in Research Day 2020 SRM University, AP• Published in IRPH. Extracurricular And Leadership

Tele – Hawks Graduate Student Ambassador Nov 2022

Graduate Admissions Department IIT-Chicago, IL

• Lead several initiatives to make knowledge available to students from all around the world. Develop relationships with potential students via phone, email, text, social media, and in-person visits. Provided training and shadowing sessions to new team members. Sales Consultant Aug 2021 – Mar 2022

Herbalife Nutrition India

• Working as a sales consultant taught me how to communicate with people, and accounting was interesting. It was most rewarding when I could show someone else how to enhance their health and money. Customers were shown how to use items and manage their money.

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