Liang Chen

FPGA Design Engineer

Hong Kong

FPGA Developer with over 7 years of experience in designing and implementing complex FPGA designs. Have a strong background in digital design, verification, and implementation using VHDL and Verilog. Have worked on a variety of projects ranging from high-speed network to satellite signal demodulator and have a proven track record of delivering high-quality designs on time and within budget.

● Strong experience in FPGA/ASIC design and verification flow, Architecture, RTL coding, Functional verification, Synthesis, Gate level simulations, Static timing analysis (STA), ATPG

● Experience in the design of Xillinx Zynq-7000 Soc, Spartan3E, Lattice LFXP2-40E and Altera Cyclone III FPGA boards.

● Good knowledge in design implementation and simulation tools Xillinx Vivado, ISE, Altera Quartus, Cadence, ModelSim, Questasim, MATLAB and DSP signal processing applications. RELEVANT WORK EXPERIENCE

HyperCharge Network (Remote), Vancouver, Canada

FPGA Design Engineer

07/2020 – Present

● Led the design and implementation of a 60Msps satellite receiver that demodulates and decodes data input from LNA to obtain audio and image data.

● Designed and implemented a high-performance, low-power FPGA accelerator for the company’s flagship product to accelerate data encryption by over 10x compared with software alone.

● Developed a novel algorithm for implementing pipelined multipliers that reduced latency by 25% compared to traditional methods.

● Developed test automation framework using Python scripting language for regression testing of newly developed code modules and algorithms in order to ensure reliability before deployment into production systems.

● Documented all development activities through Git along with detailed documentation including UML diagrams, flowcharts, etc., resulting in easy maintenance and future enhancements by others on the team.

Saltagen Ventures, Hong Kong 10/2017 – 07/2020

FPGA/ASIC Design Engineer

● Developed CNN FPGA accelerator for face detection, resulting process 20 photos in 1 second.

● Designed and implemented high-performance DSP algorithms such as FFT module, exponential calculation and convolution calculation on FPGA for use in CNN accelerator.

● Reduced power consumption by ~20% through innovative clock gating techniques and improved utilization of resources.

● Collaborated with hardware engineers to develop new products based on customer requirements and specifications.

● Work with ASIC design team to debug test failures at subsystem and chip level

● Plan and develop experimental test programs to verify compliance to all applicable regulations and quality guidelines.

APSTAR, Hong Kong 06/2015 – 10/2017

Junior FPGA Engineer

● Developed FPGA based designs providing communications and motor controls for surface control electronics and Interface modules for aerospace industry for various flight programs.

● Contributed in designing individual modules, Functional simulation, code coverage, worst-case timing simulation and integrated to the top-level design. EDUCATION

The University of British Columbia, Canada

Bachelor of Science — Electrical Engineering and Computer Science TECHNICAL SKILLS

HDL & SIM TOOLS: Verilog, VHDL, System Verilog, UVM, Cadence, ModelSim, QuestaSim SYNTHESIS: Xillinx Vivado, ISE, Altera Quartus, Lattice Diamond, Synopsis Design Compiler TIMING ANALYSYS: Synopsys STA, Vivado & Quartus STA SCRIPT & PROG: TCL, C/C++, HLS, Python, LabVIEW, MATLAB LANGUAGES

CHINESE: Native

ENGLISH: Fluent