ADAM ABDELHAMIED

***** **** ******** ******, ***** 302

Reston, VA 20194

TEL: 703-***-**** (M)

adwc1x@r.postjobfree.com

PROFESSIONAL EXPERIENCE:

**/**-******* **** ******* Engineer, Surveillance & C-UAS Systems, ATSC, McLean, VA 22102

Responsible for analyzing functional needs and translating them into functional design through an established system engineer process, developing systems requirements, integrating sensors (EO/IR, Radar, DF, Jammers, Video Management systems, and Security Networks), integrating Command and Control software, defining products with control systems, and working Bid and Proposals. Also responsible for all engineering efforts associated with designing, implementing, and deploying mobile surveillance systems leading a team of engineers through all phases of execution as well as all key execution parameters: cost, schedule, and performance.

09/21-04/22 Lead Systems Engineer, BROADBAND COMMUNICATIONS, L3Harris, SLC, Utah

Support the development, design, manufacturing and integration of secure networked communication solutions (PTU/Modem).

06/20 – 05/21 Lead Systems Engineer/ Engineering Manager/ Deputy PM, CI&IDS, CTSi, Lexington Park, MD.

Support engineering services contract for a critical US Navy customer including architecture development, requirements development, program analysis, software development, and test for multiple IFF systems. Oversees detailed work plans, schedules, project estimates, resource plans, CDRLs, and status reports. Conducts project meetings and is responsible for project tracking and analysis. Ensures adherence to quality standards and reviews project deliverables. Provides guidance to project team. Recommends and takes action to direct the analysis and solutions of problems.

05/19 - 06/20 Principal Systems Engineer, Shared Spectrum Company, Vienna, VA.

Provide systems Engineering Support to a number of NOAA SPRES Projects including P4, P5, P7, and P10.

05/17 - 05/19 Independent Consultant

Enterprise Arcitect, OCTO Consulting, Reston, VA. Led Systems Engineering and Enterprise Architecture support as well as vendor oversight for the AOS-DI Project at Fort Belvoir.

Systems Analysis/Expert, Kaimetrix, RAO, DISA, Fort Meade, MD. Lead Requirements Engineer responsible for the analysis and development of business, technical, and functional processes and requirements for various DISA enterprise architecture initiatives in accordance with DoDAF, BPMN, and CMMI using DOORS and MagicDraw tools. Also responsible for requirements development, trade studies, AoA and capability gap analysis for various DISA projects on mobility, security and cloud orchestration.

Lead Systems Engineer/SW Architect, MTEQ, Fort Belvoir, VA. Lead Systems Engineer responsible for HW design and SW architecture for fixed and mobile platforms to meet customer-specified KPIs and KPRs, latency, and HW (GPU and CPU) and SW (C/C++, JavaScript, REST) application/Web requirements for memory, power consumption and footprint, Virtualization, development/integration (CI/CD, Linux, Python, Jenkins, GitHup) as well as ISA interoperability. Also, Lead SW Architect responsible for the cross-team, multi-site IGSSR program developing DODAF- based layered SW architecture using MagicDraw, managing requirements in DOORS, and developing the SW in C++ hosted on VMware virtualized HW.

04/11 - 05/17 Sr. PRINCIPAL SPECIAL PROJECTS ENGINEER, Harris/ITT Exelis, SCNS Program, Greenbelt, MD.

Provided systems engineering, design and development services including: requirements analysis, functional allocation, architecture/design, RMA and Risk analysis, and trade studies for the SCNS program. Developed and maintained various SE artifacts including SRD and RTVM and conducted reviews including SRR, PDR/CDR, and TRR.

USSCR Converter Subsystem Lead: Cognizant SME responsible for all converter subsystem development phases including specification, development, and I&T.

SGSS DSP Systems Engineer responsible for DSP element for document reviews, Watch-List Risk/Gap, and Top-Concern issue identification and disposition.

SGSS IT Security Lead responsible for development of enterprise-level security requirements, end-to-end security activities from system design through ATO, implementing computer security policies, standards, and guidelines, performing security audits, evaluations, and risk assessments in accordance with NIST 800-53A publication.

SGSS Element Lead for multiple elements including Service Management (SM), Enterprise Architecture (EI) and Fleet and Ground Management Entity Management (FGM-EM) elements responsible for document reviews, Watch-List Risk/Gap, and Top-Concern issue identification and disposition.

SGSS V&V Lead responsible for SGSS RVTM assessment.

01/10 - 04/11 Sr. PRINCIPAL SYSTEMS ENGINEER, Honeywell HTSI, NENS Program, Greenbelt, MD.

Provided systems engineering, design and development services including: requirements analysis, functional allocation, architecture/design, RMA and Risk analysis, and trade studies for the NENS program. Developed and maintained various SE artifacts including SRD and RTVM and conducted reviews including SRR, PDR/CDR, and TRR.

10/05 - 12/10 IT Enterprise Architect, IBM, SEAT, Fairfax, VA.

Systems Engineer, Provided systems engineering consulting services for different customers/applications including: requirements gathering and analysis, functional mapping and architecture, and performance assessment and modeling. Developed and maintained various SE artifacts including SRD and RTVM and conducted design reviews including SRR, PDR and CDR.

Lead Systems engineer providing technical insight and oversight, supporting technical reviews, and developing technical documents required throughout the SDLC including requirements, design, development, and ITV&V.

Infrastructure Architecture Lead responsible for systems engineering design/implementation of network communication/topology, server infrastructure, messaging and directory services, IT security and IT disaster recovery for different customers.

Solution Architect responsible for customizing e2e application solutions including HW/COTS selections, SW development, Security Architecture/Design, and Performance testing.

01/04 - 10/05 Sr. PRINCIPAL SYSTEMS ENGINEER, Raytheon, IIS, Falls Church, VA.

Provide systems engineering design and research support to the Advanced Programs group.

Architecture IPT lead: FAB IR&D project

oDesigned and developed FAB applications-prototyping system architecture and infrastructure for MANET including: core/base functions libraries for DSP, COM, and NET; service managers for spectrum awareness and self-organization; and APIs for C-IED and SIGINT applications using Component X with module implementations in MATLAB and C/C++.

oDesigned and Developed Communication Algorithms for the wireless/radio interface.

oDesigned and developed SDR-based objective demo platform including RF front-end and waveform (QPSK and OFDM) implementations using Simulink/Xilinix design flow.

Lead Systems Engineer/PI: DARPA Connectionless Networks project

oAnalyzed system requirements and conducted trade studies for energy management techniques at the PHY, MAC and NET layers

oDesigned and developed system architecture including: modulation-scaling PHY, scalable-neighborhood topology management protocol, dynamic-scheduling MAC, and hybrid routing algorithms.

oSimulated and demonstrated system performance for specific communication tasks including: data aggregation, burst data, and multicast for stationary and mobile nodes.

oAnalyzed RF characteristics and propagation for various Wireless Standards including WiMax, WCDMA, CDMA 2000, and GSM and explored their application for energy optimization.

Research Engineer, Advanced Wireless Communications Systems, IRAD Project

oConducted a trade study to investigate the effects of mobility on multimedia communication performance in Ad Hoc Sensor Networks

High band IPT lead: DARPA FCS project

oDeveloped and maintained system engineering management plan (SEMP) document

oCoordinated effort to develop systems requirements, ICDs, and test plans for integrated verification and validation (IV&V)

oCoordinated effort to address High Band performance issues.

2001 - 2004 CONSULTANT, DSP+ Consulting Group, Dublin, CA.

Provided applications, architecture, design and development consulting services to a number of Multimedia and Virtual Reality start-up companies in Silicon Valley including: RealChip Communications, HelloSoft Inc., Yvent Networks and MoNET Communications.

Provided design services including system simulation, algorithm development, and product prototyping.

Addressed critical design issues including HW/SW partitioning, resource allocation, real-time data transfer, and multi-core architectures

Focused on using Matlab/Simulink to design, map, and generate code for DSP functionality into target platform (core processor or FPGA).

Managed applications engineering group with focus on IP licensing

Coordinated SW development activities including coding, debugging and benchmarking

Developed product collaterals including applications notes, reference designs, technical guides, and training materials

Coordinated technical consultation and pre-sale and post-sale customer support activities for different design and architecture issues (including: Requirements gathering and analysis, HW/SW partitioning, Host Interface messaging, DMA data transfer and mutli-core debugging).

1999 - 2001 SENIOR STAFF SYSTEMS ENGINEER, Conexant, Newport Beach, CA.

Designed, developed, and integrated Conference Bridge architecture and its data flow between TDM and HOST sides into CSM-V12 VoIP products.

Developed reference design and SW framework for a conference bridge

Designed and developed the C interfaces (for messaging, decapsualtion, decoding, mixing, re-encoding, and encapsulation).

Developed algorithms using MATLAB and implemented Assembly code (Countach DSP) for signal mixing module (including: noise suppression, common framing and alignment, and canceling return echo).

Determined MIPS and memory requirements to estimate limits on number of participants and developed C/C++ code to allocate buffers and create objects for participants.

Developed DVT simulations to test the interfaces using C/C++ running on target evaluation boards (based on ARM9 and Countach DSP).

1998 - 1999 DSP MANAGER, Lucent, Consumer Products, Eatontown, NJ.

Managed DSP Algorithms & Firmware Group of 5 engineers.

Designed, developed, and integrated DSP algorithms using MATLAB and feature code using C and Assembly languages on ARM and DSP16xx platforms.

Developed a reference design for a Voice Dialer for 900-MHz digital cordless telephones.

1997 - 1998 STAFF ENGINEER, ITT/ACD, Secure Communications Division, Clifton, NJ.

Designed, developed, and integrated DSP algorithms using MATLAB and COSSAP and ported code into C and Assembly using C5x and C6x platforms.

Supported development of fixed -point conversion and scaling for real-time implementation of MELP on TMS320C5x and C6x platforms.

Analyzed and debugged HASH algorithms for security applications

Analyzed and developed algorithms and simulation models for modem design and multiple-access communication systems including CDMA, GSM/GPS and WiFi using MATLAB and COSSAP.

1994 - 1997 RESEARCH FELLOW, CTET, SUNY, Buffalo. NY.

Participated in technical and market research for technology evaluation and transfer

Developed several voice input/output interfaces for access and control.

Developed reference designs for digital hearing aids and cochlear implants.

Developed a number of research proposals and conference presentations.

1989 - 1994 ASSISTANT PROFESSOR, S&BME Department, LaTech, Ruston, LA.

Taught several undergraduate and graduate courses and supervised graduate research theses and undergraduate design projects.

Established and managed the DSP Laboratory including a team of 10 engineers.

Developed different speech coding, synthesis and recognition systems using MATLAB, C and ASSEMBLY languages, SPOX operating system for the TMS320C30 platform, and Neural Networks Professional II+ Software.

1986 - 1988 RESEARCH ASSOCIATE, IBM Cairo Scientific Center, Cairo, Egypt.

Participated in Arabic speech recognition and synthesis research.

Developed a multi-feature speech training system for deaf children

Participated in identifying basic speech units for Arabic speech synthesis and recognition.

EDUCATION:

1982 - 1986 Ph.D., ELECTRICAL ENGINEERING, Ohio State University, Columbus, Ohio.

1980 - 1982 M.S., ELECTRICAL ENGINEERING, Ohio State University, Columbus, Ohio.

1972 - 1977 B.S., ELECTRICAL ENGINEERING, Cairo University, Cairo, Egypt.

ADDITIONAL ACTIVITIES/TRAINING:

OPNETWORK 2005, OPNET Technologies, Washington, DC, August 22-26, 2005.

MPRG Wireless Symposium, VT, Blacksburg, VA, June 8-10, 2005

EDA Tech Forum, San Jose, CA, 2003

Xilinix’s Programmable World, San Jose, CA, 2002 and 2003

Altera’s SOPC World, San Jose, CA, 2003

TI C54 Training Workshop, TI, San Jose, CA, April 2002.

ARM Processor Training, ARM, Los Gatos, CA, March 2000.

COSSAP training Workshop, Synopsis, ITT, Fort Wayne, IN, March 1998.

Short Training Courses, Learning and Performing Center, Lucent Technologies including:

oModern Digital Modulation Techniques, August 24-28, 1998

oDSP16xx Architecture, Instruction Set and Development Tools, October 5-9, 1998

oIS-95 CDMA System for Cellular and Personal Communications, Dec 1-3, 1998

oDigital Signal Processing for Wireless Communications, January 12-15, 1999.

Special Study in Data Network Design, UCI, Irvine, CA, winter 2000.

Special Study in Wireless Communication, Stevens Institute of Technology, Hoboken, NJ, Fall 1997

KNOWLEDGE, ABILITIES AND SKILLS:

Knowledge of Decision Analysis methodologies and tools including Decision Lens software.

Experience in requirements analysis and development using ReqPro and DOORS and systems design using Rational Rose and Visual Studio.Net platforms, object-oriented software development and UML programming, configuration management tools including ClearCase and Source Safe, and defect management tools (Clear Quest), performance modeling tools (Ambience) and performance testing tools (including IT-CAM, LoadRunner, RPT/RFT, and VitalNet).

Exposure to various integrated testing, verification and validation (IV&V) methodologies and tools including System Performance Prediction, Requirements Analyze, and Requirements Testing.

Experience with RF propagation characteristics and Wireless Standards including WiMax, WCDMA, CDMA 2000, and GSM.

Knowledge of Telecommunications and Signal Processing theory and DSP implementations.

Extensive fixed-point DSP coding experience in C/C++ and ASSEMBLY on TI's C5x, Lucent 16xx, and ARM platforms as well as PC-based platforms with hands-on real-time debug skills.

Working knowledge of DSP and communications systems theory, design and simulation using MATLAB/SIMULINK and embedded software design and implementations of DSP and multimedia nd Virual Reality telecommunications algorithms.

Exposure to various EDA tools for FPGA design including Mentor Graphics’ FPGA Advantage and Precision, Xilinix’s ISE, and Altera’s Quartus II and FPGA platforms including Virtex and Stradix.

Good understanding of embedded systems design, multi-core architectures, HW/SW partitioning and real-time embedded system development, implementation and power/performance optimization for a number of platforms including Power PC, ARM, MIPS, and Intel.

Familiarity with various IDEs and SDKs including Andriod Studio, iOS Mapbox, and MS Intune.

Good understanding of network systems design, network protocols and simulation tools including OPNET.

Good understanding of DSL, VoIP, and wireless protocols, applications and standards.

Team, project and program organization and management skills (MS Project).

Knowledge of Systems Engineering methods and processes, DODAF, IPDS, CMMI and 6Sigma.

US DoD Security Clearance:

Level: Secret

REFERENCES:

References are available upon request.

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