REVANTH KUMAR BANDARI

602-***-**** • adw88q@r.postjobfree.com • Tempe, Arizona • www.linkedin.com/in/revanthkumarbandari EDUCATION

Master’s – Electrical Engineering: Electronics and Mixed signal Circuit Design. Jan 2022- Dec 2023 Arizona State University, Tempe, AZ. GPA: 3.76 / 4.00 Relevant Master’s Coursework: Digital Systems and Circuits, VLSI Design, Hardware design, Python, Machine Learning with deployment on FPGA, Semiconductor Device Theory, Analog Integrated Circuits. Bachelor of Engineering: Electronics and Communication Engineering. 2014- 2018 Osmania University, Hyderabad, India. CGPA: 8.97/10.0 Relevant Bachelor’s Coursework: Digital Electronics, Analog Electronics, Logic Switching Theory, Digital IC Applications. TECHNICAL SKILLS

Design Tools and Skills: Oscilloscopes, Cadence (Virtuoso, Innovus), Synopsys (Hspice, Design Compiler), Mentor Graphics

(ModelSim), Calibre, Waveview, IC Validator, RTL Design, Physical Design, DRC, LVS & PEX, Linux, 32nm, 25nm and 7nm PDK Technology nodes.

Programming Languages: Verilog HDL, System Verilog basics, Python, C programming. PROFESSIONAL WORK EXPERIENCE

Design Verification Engineer Intern Jan 2019- Nov 2019 Microchip (Microsemi) Corporation Pvt Ltd, Hyderabad, India.

• Design & Verification of AMBA APB-UART slave controller from scratch (no reusing).

• Understanding specifications provided by ARM, designed & verified APB UART Slave on APB based simulator with all different test cases controlled by registers, with a variable Baud Rate for 5/6/7/8-bit transceivers with/without parity bits.

• Gained handsome experience in Linux basics, RTL coding for APB, UART FSMs, debugging errors through Questasim Waveview. Internship at TIFR-Tata institute of Fundamental Research Balloon Oct 2018-Dec 2018

• ZYBO board is used to implement wireless communication system using FPGA programming Verilog HDL Xilinx Vivado tool. Internship at ECIL (ELECTRONICS CORPORATION OF INDIA Ltd) June 2018-Aug 2018

• Worked on automation of toll gate using RFID which is successfully implemented on 8051 Microcontroller. PROJECTS

Design of RTL to GDSII ASIC Design: Acceleration for Graph Convolution Neural Networks (GCNs) Fall 2022

• Verilog code for the GCN module is written and verified the functionality using ModelSim HDL simulator.

• Synthesized the design using Design compiler and verified its functionality. Performed APR using Innovus and imported the GDS file into Virtuoso layout. Performed DRC/LVS checks on the final layout, and Power analysis. Design of 16x16 Register File (Cadence Virtuoso, 7nm PDK FinFET) Fall 2022

• Designed a 16x16 Register File with one read and write port by using given 16x1column group and bit cell.

• Designed schematic and layout of 4-16 decoder using RVT devices that will drive the corresponding word lines and gates were sized using logical effort, verified functionality, and checked DRC and LVS clean.

• Generated the design of 16x16 RF array and integrated it with a decoder and verified the final functionality. Design, synthesis, and layout of 2bit Adder using APR (Cadence Innovus,7nm PDK FinFET) Fall 2022

• RTL Code and simulation using ModelSim and synthesized using Design Compiler, generated Timing, Area, and Power reports. Performed floor and power planning, placement of standard cells and clock tree synthesis, etc., using Innovus.

• Static timing Analysis on post-placement and routing. Imported GDS into virtuoso and performed DRC and LVS on the final layout. Post simulations to ensure the design meets performance and specifications. Design, layout, verification of an NAND2px5_ASAP7_75t_R (Cadence Virtuoso, 7nm PDK FinFET) Fall 2022

• Designed & verified the NAND gate and performed pre-layout and post-layout simulations using Hspice and PEX extracted netlist.

• Layout was matched with 7.5 track cell library architecture and minimized area.

• Performed DRC, LVS, PEX using Calibre for functional verification, and calculated rise and fall time delay. Design of 4-bit Adder and 1-bit Adder, NAND2, NOR3 gates (Cadence Virtuoso, 32nm PDK MOSFET) Spring 2022

• Designed, developed schematic and layout of 4-bit adder using 1-bit adders following mirror structure in cadence(virtuoso) environment. MOSFETs were sized using logical effort to optimize delay.

• DRC, LVS checked calculated rise & fall time, and high-to-low and low-to-high propagation delays using Hspice. Design Simulation, Analysis of Low-Dropout Regulator (Cadence Virtuoso, 25nm PDK) Spring 2022

• Amplifier is designed using the Current Mirror, given to construct driver stage to have specified current flow to output.

• Calculated resister values which are used in voltage divider in order to get input feedback, using miller compensation circuit is made stable. Then performed DC analysis, AC analysis, transient load and line regulation with step change of load and input. Design of Miller Compensated Operational Amplifier (Cadence Virtuoso, 25nm PDK) Spring 2022

• As per design specifications max unity gain frequency, min power consumption, DC Gain and Phase Margin were achieved.

• Biasing circuit is built and performed AC, DC, Transient analysis Then plotted Gain vs frequency and Phase vs frequency plots.

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