John Bridge

603-***-****

advoon@r.postjobfree.com

Derry, New Hampshire

Senior Hardware Design Engineer with 20+ years experience in the microprocessor design industry. Skilled in RTL System Verilog Design, Debug, and verification tools. Ability to provide guidance to junior team members for RTL design. Focuses on fast turnaround of bug fixes for all his internal customers. Strong team commitment. Doing all possible to help the team meet deliverable schedules. Skills/Tools RTL Design, Verilog, System Verilog, RTL Design, State machine design, Data Path design, arbitration design, Functional Verification, VLSI, ASIC, Collage, Synopsys Verdi, Synopsys VCS, Spyglass, Lint, SGLINT Super Lint, VC Lint, LEC, SGDFT, SGCDC, SGOL, PowerArtist, writing assertions, deleting and/or waiving deleted sequential, timing constraints, SAI (Security Attributes of Initiator), DFx Secure Plugin

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Experience Intel, Senior Design Engineer, 2001-Present 2019-present Intel OOBMSM (Out-of-Band Management Service Module) Designed SRAM Interface. Wrote RTL to write back ECC correction data to SRAMS. Generated MBIST logic. Designed Telemetry Instruction Decode and Streaming logic. Added IOSF interface to streaming logic. Added logic to detect incoming IOSF-SB secondary bus resets. Debugged functional bugs. Setup R2G tools. Tools owner for project. Remove dead code in OOBMSM. Debug SGLINT and add waivers when needed. Debugged Super Lint and added waivers when needed. Reduced tool waiver files. Jasper Debug. Expanded VISA coverage. Added next Gen VISA feature. Added interface to DVP (Debug and Validation Platform). Added and maintained sub Ips (IOSF EP,

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2016-2019 10nm RTL design Ubox IP. Responsible for all aspects of M2ubo design, from RTL feature coding, debug, bug fixes, and physical implementation. Team expert on all functionality related to the mesh interface. Supported all ingress and egress credit logic changes, including associated RF changes and updates for ingress and egress queuing. worked closely with validation to create tests to ensure that all m2ubo ingress/egress buffer conditions — empty, full, and overflow. Created and updated m2ubo assertions to help with m2ubo debug and was responsible for physical timing issues, logic clean-up, pruning unused logic, as well as paranoia reviews. Delivered good quality RTL as measured by the low bug rate. Provided timely delivery of all functional changes to m2ubo and bug fixes to meet Ubox and program milestones. Worked independently with various teams (arch, val, tfm, clocking, dft, dfd) and resolved all open issues related to m2ubo. Increased Ubox DRNG performance from 0.97GB/sec (SKX) to 2.5GB/sec (product landing zone requirement). 2014-2016 Helped architect, wrote the MAS, and designed and implemented the RTL for the companion die interface. Architected a IOSF-SB Ring to replace critter changed. Made presentation to the Misc. and CR work group detailing the IOSF_SBE replacement for critter to be use in M2IOSF and MC. Architected a way to use multiple register interfaces for IOSF- SB Endpoint. Design used in multiple IP’s.

2010-2014 Responsible for the RTL development and debug of the Poulson Clock system including the filter, uncore, core and IO PLLs. Member of cross-site clock architectural team meetings with Fort Collins physical clock team and validators. Helped develop the clock system specification MAS. Reviewed and resolved assertion-based validation issues. Held RTL global design reviews for functional flows (power up/cold reset, warm reset, burn in, ratio changes), debug features 1 (fuse overrides i.e., fixed DCA codes, fixed ratios, observability), debug features 2 (bypass and ODCS), duty cycle correction and detection, and deskew and distribution.

2005-2010 Logic designer on the Tukwila and Whitefield Pbox project responsible for Pbox functionality of the interconnect built-in self-test (Ibist), and data path, deskew buffer and control, which includes deskew buffer, latency buffer and deserializer, and Ibist related registers. Leader of the MMDC Tukwila fault grade functional content group lead for DPM defects per million testing.

2001-2005 Logic designer on Tanglewood Ebox design. Designed pipe stage for the arithmetic unit, playback, and memory interface logic. Awards Recognition for exemplary cross-site performance driving Pbox to achieve TMVV milestones. Recognition for driving and sustaining less than ten pending functional bugs on Pbox and for limiting the bug lifetime to less than two weeks.

Recognition for addressing 150 functional bugs during clock dungeons resulting in FEV clean clock fubs and a clock MSV Model coming out of reset Recognition for defining and delivering DDR SAI feature implementation via CRI on time for Op5 milestone and for reuse by HBM and GEN3 teams

Recognition for work in converting the SKX iMC critter collateral into the 10NM IOSF-SB standard

Recognition for demonstrating high degree of resiliency in tacking multiple priorities for OOBMSM IP across A0 bugs, B0 features and supporting power-on request. Recognition for focusing on delivering results for the customer, being a team player and willing to do anything to get the job done, as well as being independent and able to work architecture designs through to implement RTL

Education New Hampshire Technical Institute Associate in EET