Chau Nguyen

**** ********* ***** *** **** CA ****8 Cell: 408-***-****, email: adv6af@r.postjobfree.com

OBJECTIVE: Senior Mask Layout Designer

. My specialty is in the area of RF/analog/Mix Signal IC layout design.

. Experience of physical layout design and taping out ICs in advanced silicon CMOS (7nm, 65nm to 90nm) processes using Cad tools from Cadance Virtuoso, and Calibre Assura, PVD, Hercules, lpe and Klayout .

. Work involved layout from block to chip level design multi-Gigabit fiber optic transceivers (TIA, Laser Driver,PLL,banggaps and CDR,Equalizer) Mixed signal chip.

. Layout advanced Serdes and other analog and mixed sinal marcros in deep nanometer –

Level Fin Fet technologies.

EDUCATION: Evergreen Valley College -- US of California – AA 1999

Silicon Drafting Institute, Santa Clara -- IC layout Course1999

Advance Mask Layout Design course – San Jose City College 2001

EXPERIECE:

BROADCOM CORPORATION LIMITED San Jose/CA

Senior Mask layout designer 4/2012 to 8/2022

. Perform and support all layout works from CMOS cells, block up to compete chip level.

. Focus on Analog layout design for best performance and optimal space utilization by applying

analog layout techniques like matching, shielding, emphasizing critical device and signals together

with an excellent floor planning to produce best layout possible.

. Floor planning custom layout from chip level with block, RF Mix signal analog to digital, area estimate, power grid placement, pad placement, ESD structure, critical matching technique, signal sealing for noise and coupling in various types of analog mix signal circuitries.

` Familiar with layout analog circuits such as op-amp, voltage regulator, buffer to build Datapath, TIA&CDR, TX &RX, Sensor ADC,PgPOR and decaps of 28GB for Fiber Optic group.

Assemble chip top level including padframe analog and digital section, powers bus &signal inter-connections. Verification run drc,lvs, erc,esd, antenna and density . Delivery final data to fab.

. Work closely and understanding very well design engineers need and demands, interact within team members to produce the best layout for circuit.

MAXIM INTEGRATED CIRCUIT INC. Sunnyvale/CA

IC Layout Designer 8/2001 to 6/2011

Estimate Layout schedule, floor planning custom layout of analog and digital circuit of Maxim in house processes, hierarchical layout cell design from transistor level to top level IC die assembly, chip top level routing and interconnect, draw layout to achieve logic function, critical signal and power bus with optimum resistance.

. Custom Layout BIPOLAR, CMOS, and BICMOS technologies.

. Draw layout for sub-micron processes (in houses processes, TSMC 28nm) for Maxim projects (application: video, power, and data convert).

. Run layout verification DRC and LVS using ASSURA and DRACULA in CADENCE environment and CALIBRE environment, cell level verification and parasitic extraction to minimize the impact on the design performance.

REFERENCES

Available upon requested!

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