MICHAEL J. HAUSER

*** ****** **. #*, ****** NY **208

adv2oe@r.postjobfree.com

802-***-****

PROFESSIONAL SUMMARY

Published senior semiconductor device engineer with exceptional skill in Research and Development and over 20 years of experience in the semiconductor industry. Guest speaker and publication review board member for IRPS, IEDM, ISMI, and TRC. Highly skilled in data analysis, technology development, manufacturing processes, quality control, and reliability. Specialize in reliability physics of device wear out mechanisms, RelXpert simulation design and development for product life-cycle evaluation, manufacturing process oversight, and JEDEC compliance. With excellent communication skills has collaborated with fortune 500 customers to assess, design, and resolve fault isolation for required product performance. Team leadership skills enabled the development team and design team to achieve improvements in robust, quality, and reliable products.

EXPERIENCE

2015 – 2023 GlobalFoundries, Malta, NY – Principle Member Technical Staff

Perform semiconductor process development reliability to better assess device degradation and improve product lifecycles.

Coordinate manufacturability readiness evaluations

Design experiments and program analysis software, to evaluate fabrication process robustness of MOSFET (FINFET) and Bipolar devices in bulk Si, SOI, and SiGe technologies to achieve manufacturability for Tier 1 customer applications.

Develop statistical models which describe key performance characteristics, enabling customers to assess failure rate, and tune key performance across the product lifecycle.

As the lead technical RelXpert expert, oversee simulation modeling for product development kit to ensure accurate reliability analysis to meet customer requirements for mission-critical applications/technologies.

Board member - Assess manufacturing line faults and recommend corrective action which protects customers from faulty hardware and retains revenue when appropriate screening is assigned – improves tool monitoring, contributes to GF quality, and improves customer satisfaction.

As the RelXpert enablement “champion” for all GlobalFoundaries technologies I was responsible for the following key initiatives that resulted in significant value add/design improvement/cost- savings/reduction in time-to-market leveraging GF’s ascent in the semiconductor market space. 2

o Provided training on enablement requirements

o Applied problem solving for unique features, innovations, and new methods in technology and applications

o Insured the implementation of best practices in FABS and technologies

Using AGILE PLM, effectively worked with technology development teams for the product lifecycle management which drives efficient development cost management, comprehensive and standardized key customer facing documentation, and improved manufacturing line controls. 1999-2015 IBM, Essex Junction, NY – Senior Engineer

Collaborated closely and provided key input with Cadence® software development team to develop present day RelXpert®.

Performed microelectronics Reliability assessment and qualification.

Design structures, experiments, and analysis, to evaluate fabrication process robustness of MOSFET devices in bulk Si, SOI, and SiGe technologies to achieve manufacturability for Tier 1 customer applications.

Developed mathematical models which describe key performance characteristics

Programmed simulation modeling for product development kit (PDK), design rule checker (DRC), evaluate layout (Skill).

Lead Project mgr silicon germanium technology for RF applications EDUCATION

2006 Master of Science in Electrical Engineering with a concentration in semiconductor device physics and opto-electronic devices. MSEE, Walden University

1999 Bachelor of Science in Electrical and Electronics Engineering with 1 year research in porous silicon substrates, research assistant in MOSFET device practicum, and graduate level course work. BSEE, Purdue University

TECHNICAL SKILLS

Cadence design and simulation tools

C programming

JMP

Mathematica

Matlab

Perl

3

Python

SAS

SPSS

HSpice®/Spectre®/RelXpert®

Visual Basic

Java

Windows/Linux/Unix

bsh, ksh tcl

Oracle Agile PLM

Microsoft Office

PATENTS

Michael J. Hauser, Mike Zierak, Inventors; GlobalFoundries US Inc, assignee. Process Induced Damage mitigation ….United States Patent, US pending ., 2022-2023..

John J. Ellis-Monaghan, William M. Green, Michael J. Hauser, et. al., Inventors; GlobalFoundries US Inc, assignee. Integrated LDMOS devices for silicon photonics. United States Patent, US 9,304,335. April 5, 2016.

Ethan H. Cannon, Michael J. Hauser, Timothy D. Sullivan, Inventors; GlobalFoundries Inc, assignee. Structure and method to ensure correct operation of an integrated circuit in the presence of ionizing radiation. United States Patent, US 9,223,037. December 29, 2015.

John J. Ellis-Monaghan, Michael J. Hauser, et. al.,, Inventors; GlobalFoundries US Inc, assignee. Fabricating polysilicon MOS devices and passive ESD devices. United States Patent, US 9,087,808. July 21, 2015.

David G. Brochu, JR., John J. Ellis-Monaghan, Michael J. Hauser, et. al., Inventors; GlobalFoundries Inc, assignee. Dual L-shaped drift regions in an LDMOS device and method of making the same. United States Patent, US 9,059,281. June 16, 2015

Timothy H. Daubenspeck, Jeffrey P. Gambino, Michael J. Hauser, et. al., Inventors; International Business Machines Corp, assignee. Thermal via for 3D integrated circuits structures. United States Patent, US 8,933,540. January 13, 2015

John J. Ellis-Monaghan, Michael J. Hauser, et. al., Inventors; GlobalFoundries US Inc, assignee. Back- End-of-Line Metal-Oxide-Semiconductor Varactors. United States Patent, US 8,809,155. August 19, 2014.

Ethan H. Cannon, Michael J. Hauser, et. al., Inventors; GlobalFoundries US Inc, assignee. Array of alpha particle sensors. United States Patent, US 8,647,909. February 11, 2014.

Wagdi W. Abadeer, Michael J. Hauser, et. al., Inventors; GlobalFoundries Inc, assignee. On demand circuit function execution employing optical sensing. United States Patent, US 7,915,571. March 29, 2011.

Ethan H. Cannon, Michael J. Hauser, et. al., Inventors; GlobalFoundries Inc, assignee. Design structure for alpha particle sensor in SOI technology and structure thereof. United States Patent, US 7,875,854. January 25, 2011.

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Ethan H. Cannon, Michael J. Hauser, et. al., Inventors; GlobalFoundries Inc, assignee. Method for detecting alpha particles in SOI technology. United States Patent, US 7,550,730. June 23, 2009. PUBLISHED ARTICLES AND BOOK CHAPTERS

M. Hauser, et. al., "Parasitic Drain Series Resistance Effects on Non-conducting Hot Carrier Reliability,” 2022 IEEE International Reliability Physics Symposium (IRPS), Dallas Tx, 2022.

C. Van Dam and M. Hauser, "Ring oscillator reliability model to hardware correlation in 45nm SOI," 2013 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 2013, pp. CM.1.1-CM.1.5, doi: 10.1109/IRPS.2013.6532061.

S. Mittl, M. Hauser, et al., "Reliability characterization of 32nm high-k metal gate SOI technology with embedded DRAM," 2012 IEEE International Reliability Physics Symposium (IRPS), Anaheim, CA, 2012, pp. 6A.5.1-6A.5.7, doi: 10.1109/IRPS.2012.6241866.

D. P. Ioannou, M. Hauser, et.al. "A robust reliability methodology for accurately predicting Bias Temperature Instability induced circuit performance degradation in HKMG CMOS," 2011 International Reliability Physics Symposium, Monterey, CA, 2011, pp. CR.1.1-CR.1.4, doi: 10.1109/IRPS.2011.5784559.

Zhenrong Jin, J. D. Cressler, W. Abadeer, Xuefeng Liu, M. Hauser and A. J. Joseph, "Hot-carrier stress induced low-frequency noise degradation in 0.13 /spl mu/m and 0.18 /spl mu/m RF CMOS technologies," 2004 IEEE International Reliability Physics Symposium. Proceedings, Phoenix, AZ, USA, 2004, pp. 440- 444, doi: 10.1109/RELPHY.2004.1315368.

R. W. Mann, M Hauser, et al., "Ultralow-power SRAM technology," in IBM Journal of Research and Development, vol. 47, no. 5.6, pp. 553-566, Sept. 2003, doi: 10.1147/rd.475.0553.

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