Design Intern Research Associate

SHARATH REDDY MUDIAM

********@***.*** +1-602-***-**** Linkedin

SUMMARY

ASU graduate student with work experience as an engineer and a strong background in Digital design, Physical Design, VLSI Design and in semiconductor industry looking for new grad roles Starting from May 2023 to learn new skills and utilize my current skills. EDUCATION

Master of Science in Electrical Engineering, Graduating May 2023 Arizona State University, Tempe, AZ CGPA: 3.80/4

Relevant Coursework: VLSI Design, Constructionist approach to Microprocessor Design, Digital System Circuits, Python for Rapid Engineering Solutions, Analog Integrated Circuits, Nano Fabrication, Linear System Theory, Introduction to Autonomus Vehicles. Bachelor of Technology in Electronics and Communication Engineering, 2016 - 2020 Vellore Institute of Technology, Vellore, India CGPA: 8.28/10 SKILLS

Programming Languages: Verilog, Python, Tcl, Shell Scripting. Development Skills: Floor-planning, placement, clock tree synthesis and routing, setup, and hold, HSPICE, CMOS, ARTS. Hardware/Tools/OS: Cadence Virtuoso, Innovus, Synopsys Design Compiler, Primetime, ModelSim, Calibre (DRC, LVS, Pex), MAT- LAB Simulink, Static Timing Analysis, IC Validator (Layout), Windows, Linux. EXPERIENCE

Arizona State University: Graduate Research Associate Jan 2023 - present

• Working on RTL to GDSII development (28nm) of Alphacore’s phase delay flash counter. Intel Corporation: Physical Design Enablement Intern Jul 2022 -Dec 2022

• Worked closely with a team to find the optimal NB CPU/memory values of the 1278, 1222 test cases by using ARTS.

• Developed the shell scripting that is used to extract run data from ARTS runs.

• Physical Verification training experience in Standard Verification Rule Format and Tcl Verification Format (SVRF/TVF) coding for Design Rule Checks (DRC).

VLSIGURU: Physical Design intern Jan 2022 - Jul 2022

• Designed a complex processor sub-module (block level) with 4 clocks, 140K gates, 40 memory (macros), and 1200 I/O pins, utilizing 28nm TSMC technology with 9 routing layers.

• Involved in creating Floor Planning, Power Planning,Running placement, Clock tree synthesis and Routing.

• Timing fixes (setup and Hold) pre-CTS and post-CTS including.

• Analyzed and resolved Congestion issues by proper blockages and avoiding STD cells under power straps ACADEMIC PROJECTS

ASIC Acceleration for Graph Convolution Neural Networks (GCNs) using 7nm PDK. Spring 2022

• Designed a GCN module using Verilog code and verified its functionality.

• Synthesized the verified Verilog code using DC compiler and performed automatic place and route (APR) using Innovus

• Post APR GDSII extraction and imported it into virtuoso and performed DRC, LVS check. Power measurement using Innovus. RTL to GDSII ASIC design: Two bit adder using Cadence Innovus tool (7nm PDK) Spring 2022

• Implemented Verilog code for 2-bit adder and verified funtionality in ModelSim.

• RTL was synthesized using Synopsys Design Compiler and performed automatic place and route (APR) using Innovus.

• Post APR GDSII extraction and imported it into virtuoso and performed DRC, LVS check. Four Bit Adder Design using 32nm CMOS pdk Fall 2021

• A four-bit adder was designed which minimized area, power, and delay. Initially a one-bit adder was designed, which used mirror architecture and carry ripple adder architecture was used for the design of four-bit adder. Sizing of transistors.

• Transistor level schematics and layout were drawn using cadence virtuoso tool and DRC, LVS was cleaned.

• Achieved a worst-case delay of 96.2ps, power of 67.79uW, and an area of 31.42um2. Standard Gates Design and Development using both 7nm FINFET and 32nm CMOS PDK Fall 2021

• Designed and developed schematic and layout of Inverter, NAND, NOR, and XOR using Cadence Virtuoso.

• Performed Transient and DC analysis using HSPICE and waive viewer tool was used to view the simulations.

• Designed 3x3 layouts for NAND, NOR. Running DRC and LVS checks and debugging the errors. Parasitic extraction (PEX) of the layout using Xact 3d for post layout simulations.

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