Processor Embedded Software

Vijay Janarthanan

Embedded Software Engineer

HIB – valid stamping till Oct 2024

Email: *****.***@*****.***

Mobile: +1-347-***-****

SUMMARY

16+ years of Work Experience in the field of Embedded Software development and have worked with various Micro-processors/Micro-controllers, involved in software full phase development cycle, Code development in Embedded C, Linux Device drivers, RTOS, Kernels, networking, Socket programming and shell scripting.

Hands on Experience in bootloaders such as UBOOT/PMON, Board Support Packages (BSP) customization and porting for various platform architecture and extensive experience in Board Bring-up, Diagnostics, and Post silicon validation (PSV).

TECHNICAL SKILLS

Programming languages: Embedded C and C++

Operating systems: Linux and windows

RTOS: ThreadX and FreeRTOS

Microprocessor/Controllers: OMAP 4460, (ARM cortex A9, A53), Intel Baytrail, STM32 series, TI Hercules TMS320 and RM48, Wintegra Networking processor, and IMX6 NXP

Bootloaders: Uboot, WinMon (PMON)

Protocols/bus: PCIe 3.0, USB 3.1, CAN2.0, 10G Ethernet (XGE)

Serial interface: I2C, SPI and RS485 UART

IDE: CCStudio, Andes IDE, KEIL uVision and IAR workbench

Static Analysis tools: CPPCheck and Coverity

Repository: SVN, GIT, Perforce and Bitbucket

Protocol Analyzer: Anritsu (Ethernet) and Keysight (PCIe)

JTAG and ICD: ST Vlink, J-link, Greenhills MultiIDE

WORK EXPERIENCE

HCL Technologies Ltd

Technical Lead (Embedded Software) 2006 – Present

Involved in various projects domains such as Semiconductor, Industrial, Consumer Electronics Telecom and Automotive domains

Executed the full software process flow such as requirement analysis, software architecture, design, development with verification and validation of the Embedded products

Worked in various customers and locations such as USA, Japan, China and Australia.

Projects Experience

Title: Calibration for Digital Instruments

Company: Teradyne (Contract) – April 2022 till Date

Language: Embedded C++

OS: Windows Visual C++ 2010

The Digital instruments are used for validation of the silicon chips. There are different instruments which are made as a PCB card and that digital card contains multiple chips where in it resides with Embedded Microcontrollers and other analog and digital

circuits. The calibration is done for all the analog and digital part of the board using a C++ Application.

Role and Responsibility:

● Design and development of Single Ended /Differential comparator calibration strategy

● Voltage VHH High voltage DAC calibration strategy

● Embedded Test APIs to interface with application and Embedded HAL Drivers

● Embedded Calibration test framework for the performance validation of the FPGAs.

Title: Fire Detector & Panel Interface Loop Card

Customer: Honeywell - Jan 2020 till Feb 2022

Language: Embedded C

Hardware: STM32 and TI RM48

Tools: CCStudio and Cube suite

Description:

The product does an interface with the VESDA detectors to the IDNet fire loop panel.

The firmware development here to interface the detectors and the fire panel using the define protocols format such as EBUS and 3PII which lies above the RS485 UART interface. Due to limitations in the quantity of data than may be transferred to and from the 3PII and the complexity of the VES smoke detector compared to the VEP and VEU models, the VES interface had used multiple 3PII modules which needs to be handled by the EBUS protocol appropriately

Role and Responsibility:

BSP porting for the STM32 microcontrollers

Drivers for RS485, ADC

EBus data packet formation and validation

System validation and testing

Transfer Jet- High-Rate Close Proximity (HRCP)

Customer: Sony & JRC Japan – Nov 2018 till Dec 2019

Language: Embedded C

Processor: Andes RISC V core

OS: FreeRTOS

Description:

The Transfer Jet device contains various interfaces such as USB, UFS, PCIe, RF wireless and XGE protocol. The SOC chip is integrated with Andes RISC V core 32 bit which runs an FreeRTOS. The device is mainly used for data transfer for various scenarios such as ticket gate, camera interface data logger. The PSV validation is done for interfaces such as PCIe 3.0 and XGE.

Role and Responsibility:

Device driver development for the PCIe Gen 3 End point driver.

POST silicon validation for Andes RISC V

Pre/Post silicon validation for PCIe and XGE interface

Debug support and triage for the PSV issues.

Test automation for PCIe and USB interfaces.

IP7 – Remote Display

Customer - Philips Invivo( Orlando FL)– April 2018- Oct 2018

Language: Embedded C

Processor: NXP - IMX6

OS: Linux Yocto Rocko

Description:

The IP7 will be a remote display to medical devices inside the MRI Suite. While the patient is being scanned in the MRI bore, the room is not accessible unless the room is opened. The IP7 is operated primarily outside the MRI system room, in the control room. The IP7 can also be operated in a recovery room or a patient preparation area. The host patient monitor is placed inside the MRI with the patient. This use case necessitates that a remote display is available for anesthesiologists and MRI technicians.

HAB High Assurance Secure boot(TPM) is an optional feature in the i.MX SOC family, which allows to make sure only software images signed can be executed on the SOC.

Role and Responsibility:

Yocto build Environment setup.

BSP porting, Device driver Development and kernel configurations.

UBOOT and Device tree structure (DTS) customization

HAB High assurance Secure boot feature implementation

Splash screen configurations

Title: Pizza Box Vending Machine

Customer : Sanmina & 24/7 ( Fremont CA) – July 2017 to March 2018

Language: Embedded C and C#

Hardware: Aeon Series Intel based chipset

OS: Windows

Description:

This project development functional software for the Pizza Box Vending Machine development. It is primarily to validate and control the pizza box Nema 17 elevator belts motors and its hall effect sensor by developing test harness using the software in C# application. All corresponding drivers and firmware shall be modified to make the Pizza vending machine to deliver multiple slices of pizza to the end user.

Role and Responsibility:

•Firmware driver for Configurating the motors and Sensor pin outs from Arduino boards using C

•Motor controller for various operations and sensor detect using C#

•Menu button customization for pizza order GUI configurations

•Testing of the elevator movement and control

•Functional implementation of pizza tray movement from elevator motor to the oven conveyor and output elevator to the exit chute.

Title: MNH Silicon Validation

Customer: Intel Corporation - June 2016 till June 2017

Language: C and C++

Processor: Arm A53 Application processor

OS: Linux

Server: Zebu server

Description:

The MNH silicon is interfaced with the A53 application processor. The MNH chip has Camera interface where the data from the CSI MIPI interface is captured and sent to the Application processor which will display in the Video interface. The objective is to validate the silicon both Pre and Post silicon validation is done.

Role and Responsibility:

•Device driver customization for the MIPI interface

•Test framework development for the MIPI both Pre silicon and Post silicon

•Pre-silicon testing for MIPI interface using Zebu server in C++

•Post silicon validation for the CSI MIPI interface

•MIPI interface module lead and client interaction

Title: General Purpose Processor Board

Customer: Sabtech IXI – July 2014 to Feb 2016

Language: Embedded Linux Yocto Daisy

Hardware: Intel Baytrial

BIOS : Insyde BIOS(UEFI)

The GPP board is part of Sabtech’s scalable compute platform for industrial and commercial customers. The GPP is based on Intel Corporation’s latest generation Atom processor family the E38XX also known as BayTrail. In addition to the E38XX processor the GPP incorporates the latest FPGA technology from Altera. The first instantiation of Sabtech’s scalable compute platform is a 3U VPX form factor GPP board. The VPX form factor provides a compact, rugged and scalable board tailored for the commercial/industrial markets. The GPP conforms to the OpenVPX standard, ANSI/VITA 65.0, which allows interoperability with a variety of COTS solutions from other vendors

Responsibilities:

Development of High-speed interface drivers for PCIe, Ethernet (1Gb)

Development of CAN drivers for the IP core.

Serial driver for the UART, I2C, SPI

Title : Automate Mirror

Customer : Dejai ( Melbourne Australia) ( Nov 2013 till June 2014)

Language: C

Processor: LPC 3250

IDE: Keil uVision 4.7

Description:

The Automate Mirror is an easy to fit in-vehicle automotive rearview mirror incorporating multiple functions to enhance safety of road users and provide features that bring benefits to fleet operators. These include Bluetooth, Smartcard reader, Embedded Toll Tag and GPS wireless functionality.

Role and Responsibility:

•Device driver development for the Toll Tag module

•BSP porting and customization

•Development of test suite for the EOL and PAT fixtures

•Bluetooth configuration Interface

•GPS Sierra wireless configuration using AT commands

Title: Tablet PC

Customer: Matschunichi – Nov 2011 till Aug 2012

OS: Linux

Language: C

Processor: OMAP 4460(Arm cortex –A9)

Description:

The Tablet PC is a low-cost module with the Android ICS and has most of the features available in the tablet segment. The project is mainly based on porting of the Linux

device drivers for the hardware available in the board. The device drivers are customized for the battery charger and PMIC and GPS module.

Role and Responsibility:

•Board bring up and diagnostics.

•BSP and Kernel customization.

•Driver Customization, integration and configuration for Battery charger

Audio codec and PMIC and Kernel configurations

•Unit testing and integration testing.

•Preparation of test document and test plan

Title: DSMC( Image Slice processing)

Customer: Red Digital (Los Angeles) Feb 2009 till Oct 2011

Environment: ThreadX – RTOS

Language: C

Tools: Green Hills - Multi IDE

Description:

The DSMC is a modular camera system designed to provide the highest available image and sound quality for motion picture, networked video and stills imaging applications.

This camera was built into various modules using ASIC and FPGAs and interface protocol, ISP processing for the images are configured and validated.

Role and Responsibility:

•Requirement analysis, System Design, System Development,

•Unit testing and integration testing.

•Configuration and testing of image pattern for the Image slice processing module

•XAUI controller configuration for bridging between IOB and ISP

•Preparation of design document and test plan

EDUCATION

Bachelors in Electronics and Instrumentation Engineering

1998-2002, Bharathidasan University,

Tamilnadu – India

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