Software Engineer Processor

SHIVA PRASAD ANJANAPPA

*******@****.*** 984-***-**** https://www.linkedin.com/in/shiva-prasad-anjanappa-64604016b/ EDUCATION

North Carolina State University, North Carolina, USA August 2022 – May 2024 Master of Science, Computer Engineering

Relevant Coursework: Microprocessor Architecture, ASIC and FPGA Design, and Architecture of Parallel Computers Upcoming Coursework: Neural Networks, ASIC Verification, and Advanced Microprocessor Architecture Visvesvaraya Technological University, Belgaum, Karnataka, India June 2015 – July 2019 Bachelor of Engineering, Electronics and Communication RELEVANT TECHNICAL SKILLS

• Programming languages: C, C++, Python, Verilog HDL, MATLAB, RTL, Embedded C, Assembly language, VHDL.

• Software: Xilinx-Vivado, Keil-Microvision, ModelSim, Synopsys, GIT, Bitbucket, IBM Rational DOORs, JIRA, ECU Test Tool. RELEVANT PROJECTS

• Cache Design, Memory Hierarchy Design (C++): September 2022 Implementation of cache and memory hierarchy simulator and compare the performance, area, and energy of different memory hierarchy configuration.

1. Better understanding of WBWA policy for L1 and L2 Cache along with Stream-Buffer (prefetcher). 2. Analyzing Area, Energy, and Performance using parameters like Average access time, Miss penalty, and Miss Rate.

• Open MPI, MPI, Hybrid parallel programming (C++): September 2022 – October 2022 Vector Addiction, Matrix Addition, and Matrix Multiplication implementation. 1. Working of Message Passing Interface and Shared Memory Model with different methods of implementation of the same. 2. Evaluation of behavior of both configurations along with Hybrid variant by varying threads and processors quantity.

• Branch Prediction (C++): October 2022 – November 2022 Construct Bimodal Branch Predictor, Gshare Branch Predictor, and Hybrid Branch Predictor and evaluate different configurations of branch predictions.

1. Evaluation of Bimodal Branch Predictor of different counter size and observe behavior of misprediction rate for the same. 2. Evaluation of Gshare Branch Predictor of different sizes along by changing size of global branch history and observe behavior of misprediction rate for the same.

3. Implementation of both Bimodal and Gshare branch predictor in Hybrid Branch predictor.

• Coherence Protocol (C++): October 2022 – November 2022 Implementation of MSI, MESI coherence protocol along with Snoop filter. 1. Evaluation of BusUpgr and Cache-Cache transfer for coherence protocol. 2. Understanding on Useful and Wasted Cache for Snoop Filter.

• Deep Neural Network (Verilog HDL): November 2022 – December 2022 Implementation of Convolution with ReLu, and Max Pooling. 1. Working knowledge of SRAM for both storing and reading data. 2. Implementation with minimum area and timing.

• Dynamic instruction scheduling (C++): November 2022 – December 2022 Implementation of simulator for Out-of-order superscalar processor that fetches and issues multiple instructions per cycle. 1. Understanding of Fetch, Decode, Rename, Register Read, Dispatch, Issue, Execute Writeback, and Retire functionality along with Issue Queue, Reorder Buffer (ROB), and Architectural Register file (ARF). 2. Understanding of RAR, RAW, WAR, WAW hazards along with structural hazards associated. PROFESSIONAL AND LEADERSHIP EXPERIENCE

Employer: Robert Bosch Engineering & Business Solutions Private Limited, Senior Software Engineer August 2019 – July 2022

• Enhanced System and Functional Testing for Radar under Driving Assistance (DA) by improvising Test Cases and Automation scripts.

• Contributed to CAT (Continuous Automation Testing): have developed and automated test scenarios for sub-modules Diagnostics, CAN communication, Monitoring, and Security testing by ECU Test Tool (Global tool).

• Tool development: generating test scripts for sub-module Diagnostics for Continuous Automation Testing using python scripting.

• C++ code Development: responsible for Environmental Data topic under Monitoring.

• Test Owner for Diagnostics: In charge of Requirement Analysis, Test Case development, Test Case Automation, Test Case Review, and Test Result Review for Diagnostic requirements.

• Project In-charge: Co-ordinate with project management on Test Plan, Estimating Timeline, CAT implementation, and record test activities for project release.

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