Raj Dharmendra Thakkar

+1-602-***-**** adu8au@r.postjobfree.com LinkedIn Tempe, AZ

EDUCATION

Master of Science in Computer Engineering (Electrical Engineering) August 2022 - Present Arizona State University, AZ, USA GPA: 3.83 / 4.00 Graduate Coursework: -

VLSI Design, Computer Architecture, Digital System Circuits, Semiconductor Characterization, Random Signal Theory, Foundations of Algorithms.

Bachelor of Engineering in Electronics and Telecommunication Engineering August 2017 – June 2021 University of Mumbai, India CGPA: 9.11 / 10

TECHNICAL SKILLS

Hardware description languages : Verilog, System Verilog Scripting/Programming languages : C, C++, Python, Tcl, Perl Hardware/Simulation tools : Cadence Virtuoso, Innovus, Synopsys Design Compiler, HSPICE, Xilinx Vivado, ModelSim, Calibre (DRC, LVS, Pex), MATLAB, IC Validator, PSpice, Eagle CAD, CST Studio, Arduino, Proteus

PROFESSIONAL EXPERIENCE

Researchwire Knowledge Solutions, India (Client- SAMSUNG) August 2021 – July 2022 Patent Analyst- Innovation, R & D Team

• Recognized gaps in technology where it is possibil to create new IP Landscape and invalidation.

• Led a large patent portfolio by identifying client's most valuable patents for assertion as well as detected all the infringing parties to those patents' framework.

• Classified patents along comprehensive technology taxonomy and then reviewed each asset in the portfolio on quantitative and qualitative criteria utilizing proprietary algorithms to find the most potential patents. ACADEMIC PROJECTS

Delay optimization and Layout implementation of a logic path using SAED 32nm PDK Fall 22

• Sized INV, NAND3 and NOR2 gates in the logic paths using logical effort to minimize delay in Cadence Virtuoso 6.

• Minimized the leakage power using RVT, evaluated using Design Rules Check (DRC) & Layout Versus Schematic (LVS). Development of Cache replacement policies using Gem5 Simulator Fall 22

• Assessed implications of different cache configurations by utilizing various benchmarks and modelled cost versus performance analysis on the ALPHA processor operated on Gem5.

• Modified cache replacement policy from Least Recently Used (LRU) to pseudo-LRU that escalated the efficiency. Design of a 4-bit full adder circuit using 32nm PDK Fall 22

• Executed a 4-bit full adder circuit with 1-bit mirror adder employing inversion logic, Optimized the design using sizing & design techniques with power=51µW, minimum delay= 103ps, and area= 32.3µm2.

• Verified the layout by performing DRC and LVS checks, simulated using Hspice testbenches and WaveView. Prediction accuracies of branch predictors in x86 architecture using Gem5 Fall 22

• Modeled state of art branch predictor models in Gem5 to visualize misprediction penalty on pipeline throughput.

• Compared the efficiency of models through standard benchmarks and custom multi-threaded payload. ASIC design of 16-to-1 Integrate and Fire (IF) Neuron [SAED 32nm PDK] Fall 22

• Designed a high performance IF neuron, that fires after a threshold, comprising of 4-bit adders, MUXs and D-flipflops.

• Performed DRC checks, LVS checks, PEX and verified the functionality utilizing post-layout extracted netlist simulations.

• Optimized area=150 µm2 also achieved a minimum delay= 700ps (top 1% in class) for post layout extracted netlist. Electromagnetic Based Fluid Sensor Spring 21

• Designed and fabricated a sensor (Resonant frequency= 2.91GHz.) using metamaterials that possesses high sensitivity and can detect change in the value of permittivity of different liquid samples and purity of liquid can be known.

• Authored and published a paper on the same in International Journal of Research and Analytical Reviews (IJRAR.ORG). CERTIFICATIONS

• Accomplished a certified course on ‘Programming in Core Java’ by CMP Infotech.

• Successfully completed a training on ‘IOT with J2ME using Python’ by ATS Learnings.

• Conducted a PCB Designing and Fabrication workshop for 100+ students at IEEE-RAIT.

• Completed an online course Python Programming: A Concise Introduction offered through Coursera.

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