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FPGA/DSP engineer

Location:
San Gabriel, CA, 91776
Posted:
December 06, 2022

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Resume:

Liyen Ho

*** ***** ******,

San Gabriel, CA *****

949-***-****

adtwgu@r.postjobfree.com

Career Objective

Seeking professional career in fields of Communication/Multimedia FPGA/DSP system design Skills

Programmable Hardware: Xilinx/Altera FPGA, CPLD

Device Debugger: GO DSP Code Composer, Visual DSP JTAG Emulator, Xilinx Dev Foundation/Vivado, Altera Quartus Prime Development, PC based Teaklite simulator Math Software : Octave, MATLAB, MATHCAD

Version Control Software : ClearCase, CVS, GIT

Language : C, C++, Assemblies, Verilog, VHDL

Tools : Audio/Speech DSP, IMX8 Yocto, NXP LSDK, OMAP OpenWRT, Android Stagefright frameworks/AOSP, OpenMAX media arch, ARM LTIB/Asm, Verilog/VHDL, Linux C/C++/makefile, TCP/IP, python, shell script Lab Equipments (Scope, Logic/Spectrum Analyzer, Sniffer, Protocol Analyzer) O.S. : Linux, Android, ThreadX, VxWorks

Status : US citizen

Major GPA : 3.77

Education California State University, Long Beach 1994 Master of Science in Electrical Engineering

California Fundamental Engineer Certification

Extended Education

UCLA engineering extension courses 09/01-12/01

Modern Application of Digital Signal Processing

Fiber-Optics Communications

Technical Summary

Communication System Architecture/Prototyping on Linux/U-Boot/ATF BSP, LTE/WIFI/Bluetooth/LayerScape/IMX8M/OMAP/XILINX FPGA, Yocto/LSDK/OpenWRT, Audio System Design/Prototyping on ADI DSP

Hand-on experience on GNU-Radio SDR, LTE, GFSK long range/OFDMA physical layer signal process/ protocol development/simulation works, TCPIP stack, low level works on bare metal env

Android Camera/Audio HAL, Stagefright/OMX media frameworks, Qualcomm MSM BSP

Extensive experience in design, simulation analysis, integration and testing of IP network based real-time embedded DSP firmware for telecomm, wireless and point-2-point link, DVB-T Altera FPGA based IP core integration for video comm link

In-depth experience in 3G wireless DSP baseband process for CDMA, W-CDMA, GSM, DVB-T/2, Wimax and WiFi.

Freescale iMXv6, TI OMAP4 Soc A/V firmware projects, works involve Linux, Syslink, Openmax, Gstreamer and proprietary A/V software designs, Wireless Tool/Extension development work on WIFI/802.11 device driver layer

QDSP algorithm/firmware on Video, Audio and Speech, Noise reduction, Echo cancellation and Speech clarity, MPEG Transport/RTP/RTCP streaming&signaling, H.264/AAC/AC3 video/audio codec algorithm work and enhancement/optimization on Linux platform

Tensilica /ARM/Teaklite/ADI DSP firmware on AAC, MP3, e-AC3, WMA and SBC standard based audio codec, I2C, SPI, I2S, SPDIF, Video Codec, Device driver/Linux kernel

Nexperia/TI DSP firmware on H.264, MPEG 4 and H.263 standard based video codec

Xilinx FPGA target HDL works on Color Filtering Array, Edge Enhancement, multi-channel DMA controller, SDIO, NAND flash and USB port controller. Professional Experience

Faraday Future

12/21 –, Gardena CA

Android Audio HAL for Automotive

Linux Sound Kernel: TDM/MM setup and extension

Android HAL: Audio from both MIC/SPKR using CAN (control/command) and A2B Home Comm/MM project: ADI RFE/Camera on Xilinx/Altera FPGA with DVB-T IP core and H.264 codec Xilinx based IP core, for potential aerial end2end video link, later shall equip sophisticated SW/FW CV based capability

Viasat Inc.

6/21 – 12/21, Carlsbad CA

Xilinx FPGA project verification

Linux Shell scripting: automated PL test frameworks Vivado Verilog debug/development: Turbo Coder/Decoder debug and test TI DSP codes porting: reuse DSP codes for FPGA setup scripting GMSK modem simulation: created octave GMSK modem simulation to debug the PL receiver

Cobham Connectivity (Transdigm Inc),

10/18 - 02/21, Prescott. AZ

System Architecture

Speech DSP: Noise Suppression/Cancellation, Spatial Sound Enhancement, Reverberance APCO P25: Gnu Radio SDR, IF Architecture refinement on FPGA, Baseband design, Network/ Channel Codec access, Vocoder

LTE/Kodiak MCPTT Server/Inet Tethering: on Yocto IMX8MQ platform with Telit LM960 Modem

Network Access Platform: on NXP LS1043A LSDK and WIFI/BT/SATA/NVME System Components

PCI-e/Ethernet/SPI/UART/I2S: on XILINX ZYNQ-ARTIX VHDL/Verilog platform WIFI/Ethernet/Gateway: on OMAP OpenWRT platform`

Carnation Communications (Sculpture Network),

01/18 - 9/18, San Gabriel

Startup Partner/Contributor

Wireless: Customized wireless high-throughput OFDMA communication system based

Wimax, LTE, Wifi, DVB-T/2 specifications, TCPIP protocol stack Command control link based upon 802.15, BT Br/Ebr specifications, Xilinx Zynq PCI-e based DMA controller, ADI 9364 RF direct conversion transceiver

Android MM:

Professional grade UHD low latency A/V codec/stream/link system based upon the proprietary wireless link system aforementioned, embedded android media framework (Qualcomm BSP, camera HAL/audio flinger, omx DL/IL/AL, H265/AAC-Eld codec, mpeg2 transport streaming, audio PP rendering, V4L2/EGL graphics rendering)

Yuneec USA, San Diego

2/16 – 01/18

Staff FW engineer/architect

ARM CM4 Firmware/Software architecture of video/command ctrl data link module for consummer/commercial graded drone design/manufacture, on both RTOS based and low level bare metals env

video: MPEG4 transport stream over DVB-T/2 video link

DVB-T/2 @ 6 mhz video link,

antenna selection diversity,

transport stream (corruption not security) protection scheme,

propriatory STC clock re-alignment over marginal link quality,

advanced stream manipulation for private data encapsulation,

transfer packet alignment over USB/SPI bus, cmd/sts info over I2C bus

both FPGA and ASIC based DVB-T solutions, work involved elimination of processor core requirement inside FPGA, moved cmd/sts info to main controller via SPI bus in order to cost down, advanced clock tree and transmission power management of high speed (direct conversion) transciever, FPGA management (such like RF Frequency selection) over a generic SPI link, thorough cmd/download/sts/handshaking comm from top

(host) to bottom (DVB-T asic) over I2C bus

control: Cmd/Ctrl propriatory messaging over GFSK data link

dual band operation over 915 (US) and 869 (EU) mhz bands,

implementation of propriatory frequency hopping scheme based upon pair ID (between controller and drone)

temperature calibation of capacitance bank for ext oscillator

two tiers adaptive channel filter for better noise performance

antenna (selection) diversity in Listen state

RSSI average/latch for link quality monitoring

CRC checksum (prior) and R.S. polynomial block code (current)

host monitoring facility for sensitity measurement

customized (load-asymmetric) time slot based packet transmission

implementation of specific messaging format for auto pilot feature ARM CM4:

firmware management

versioning,

on-chip flash

non-volatile info

boot mode,

download,

bootloading facility

cmd/sts communication over control pipe/ep on USB

video packet transportation over bulk pipe/ep on USB

embedded video bring-up processes for both FPGA and ASIC platform over I2C bus driver

Host:

unit test design and

generic operational interface with human and ARM controller

responsible for all operations initiation and presentation FPGA/CPLD:

processor core extraction to cost down,

interface re-design by pulling all ctrl/sts register access over SPI

register insertion over FPGA block RAM for non-volatile video opions

glue logic design within CPLD to interface with DVB-T asic device Sensory Inc., Santa Clara / Sculpture Network, San Diego 9/14 – 2/15

Contracted Technical Employee

Port/Integration/Optimization/Debug/Improve various DSP platforms for proprietary voice recognition engine, ARM (CM4), Tensilica/HIFI2,3,mini,iote,ep and Cyrix Logic Sculpture Network, San Diego

3/10 – 2/16 (get acquired)

Startup Partner, Individual Contributor

Proprietary low delay A/V codec design/implementation, involves optimizations and works listed below, latest H265/HEAACP IP network based codec integration for broadcast industry Video: FPGA based H.264 Rate control, Error concealment, High Profile/Inter+Intra Predictive Coding, MB-Tree/Trellis Quantization and CABAC binarization. Audio: Signal processing and enhancement such like Multi-band DRC, Equalization, Background Noise cancellation, Click detection/removal, Normalization, Phasor and Time compression/stretch

Speech: Multi-mic Wide band noise void/echo cancellation, Time Warping thru pitch search, Dynamic Range Control, Modulation and Sample Slip iMXv6: Dual core cortex A9 and Freescale proprietary video pipeline accelerator, Gstreamer low delay end to end streaming with Open Embedded/Android dev OMAP4: Prototype Panda board using Android/Angstrom Linux distro, TI Syslink/Bios- link and Openmax framework, works include control/concealment codes and buffers management upon H.264 HD full frame-rate encode/decode (IVA HW accelerated), Camera 3A, Noise Reduction, Color Space/Enhancement and real-time HD capture plus Display backend+Write back channel optimization, ARM v7 asm optimization WiFi: 802.11-n physical layer simulation, implementation & bring up, Linux driver porting

& debugging, IP Protocol layers porting & debugging. INTEL Inc., Santa Clara / Sculpture Network, San Diego 05/12 – 09/12

Contracted Technical Employee/ Startup Partner

Bluetooth Protocol/Control firmware on ARC processor

(Private startup projects)

AAC/MP2 audio codec projects on ADI DSP processors Video low delay decoder project on Intel PC platform QUALCOMM Inc., San Diego / Sculpture Network, San Diego 05/10 – 5/12

Contracted Technical Employee/ Startup Partner

Test Framework for Audio/Voice Q6 DSP Firmware

Video codec/process algorithms optimization on QDSP Audio signal process library optimization and enhancement Speech codecs assembly optimization for next gen Q6 DSP, including 4GV/AMR/EVRC/EFR/HR/V13k, Speech signal processing algorithms optimization includes DRC, NS for Speech, Wide-band, Time-warping, Sample Slip and DS interface to Pre/Post Signal Processing modules

(Private startup projects)

ARM processor based embedded firmware

ADI Blackfin fixed point DSP firmware

LTE physical layer/system simulation

Ethernet/USB control firmware/driver works

VIA Telecom, San Diego 11/08

– 02/10

Staff multi-media DSP engineer

Acoustic echo cancellation Development and Noise reduction Speech clarity algorithms design per 3GPP recommendation

Multimedia MPEG video codec, Bit Stream parser designs on ARM core Implement and Integrate AAC, MP3, WMA and SBC codec engines on Teaklite Assembly handcrafting, MIPS requirement study, Memory consumption optimization, customized multi-app code image

Maintain existing DSP simulator library, Audio path components, configurations and DSP applications

Wimax system physical layer control and baseband algorithm work Motorola, Connected Home Div, San Diego

05/06 - 10/08

Technical Staff DSP engineer

Implement and Integrate broadcast graded video/audio encoder engine on FPGA/DSP platform

H.264 video codec, MPEG Part 10 AAC, Dolby ATSC AC3 audio encoders on SMPTE and AES standards

Framework design to interface Host and DSP processors AverMedia Inc., Taiwan

12/03 - 02/06

Advanced Design Engineer

Evaluation of DSP processor candidates among ADI BlackFin 533, TI DM270 and Phillip Nexperia

Real-time MPEG-4, H.263, H.264 video encoder works Real-time G.723, G.728, G.729, G.722 speech codec works and echo cancellation (G.168) works

Philips Nexperia VLIW development/optimization for real-time video encoder Camera DSP, Color Filtering Array, Edge Enhancement and Noise Reduction development on Xilinx FPGA target,.

FPGA/HDL based development for multi-channel SPI, DMA controller, SDIO and NAND flash Controller

FW development on Cypress USB controller, embedded C51/ARM7, Multithreaded Windows based host AP development

SPAWAR SSC/SDSU Foundation, San Diego

01/03 - 09/03

Research specialist (on contract)

Automatic fouling condition estimator by neural network and statistical approaches, color pre-processing, edge detection, object boundary search and texture recognition. All projects are non-real time and matlab simulation based Morpho Technologies, Irvine

03/01 - 07/02

Communication system engineer

WCDMA baseband, OVSF sequence generation, RRC pulse shape, Frequency drift compensation, Phase rotation, Early late gate, Close loop power control, Rake fingers, Maximum ratio combining, Synchronization tracking, Soft handover simulation, Turbo codec/Interleaver.

WCDMA channel impairment simulation in Matlab, test vector for design verification, speech & audio codec (GSM full rate, MPEG, AC3),

802.11 MAC layer simulation works

Comarco Wireless / Hitachi Koki Imaging Solutions

09/99 - 02/01

Baseband DSP engineer (contract) / Member of technical staff

(Comarco) ETSI GSM baseband software simulation and DSP firmware implementation, Gaussian filter, GMSK modem baseband, fractional space equalizer, synchronization tracking, CRC/interleaver, CPLD programming

(Hitachi) Bitonal image process and compression, VxWorks PCI driver development Willowbrook Technologies, Van Nuys

06/96 - 09/99

DSP system engineer

DTMF tone detection, call progress, caller ID, voice activity detection, echo cancellation, VoIP/H.323, V.32/34/17 modem, fax image codec and G729 with TI TMS6201 MultiDSP, Cypress 09/93 - 09/96

Software engineer

Windows based DSP software design with real-time DSP hardware support, TI C30, C50, C51 EVM, DSP Research Tiger C31, Innovative Integration C32



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