Processor Digital Designer
Resume:
William H. Dittenhofer
Manitou Springs, CO, 80829
************@***.***
Education M.E.E.E. University of Virginia
B.S.E.E. Case Western Reserve University
B.S. Physics S.U.N.Y. at Fredonia
Hardware Skills FPGA RTL design with Xilinx (Vivado), Microsemi (Libero). Specialist in Zynq, experience with ARM, Arduino, Micro Blaze embedded design. Custom Embedded Processor Design, DSP, Image Processing, Software Defined Radio, IP development.
Computer Skills VHDL, System Verilog, SystemC, MATLAB/Simulink, System Generator, Vivado HLS, Vitis, C/C++, TCL, PYTHON, LINUX Eligibility US Citizen, Secret Clearance.
Experience
2021 DDS LLC FPGA Design
DSP fixed point implementation of a location algorithm resident on Zynq. This consisted of DDC, FFT, Fine Freq Estimator, Hilbert Transforms, etc. While integrating DSP into the Zynq platform, numerous flaws in DMA, Mem Control and control logic sections were unmasked. Worked with Firmware engineers to find root cause, then remedy issue. This required extensive modification. 2019-2021 Numerica Corp FPGA Design
Design, verification of Xilinx FPGA for portable Phased Array Radar. Serial Interfaces, high speed low latency control logic, SW Def Radio (Matched Filter). Implemented Micro Blaze based subsystem monitoring (both RTL design and C based control SW). Prototyped Image Processing algorithm in Zynq 7030 platform (C Firmware and RTL design). Used System Generator to prototype an Image Processing algorithm in a Zynq 7045 platform.
2018- 2019 DDS LLC FPGA Design
Design, verification for FPGA (Microsemi SOC) for GPS Subsystem. Ported design to Zynq prototype (7020) as part of an upgraded to client’s platform. Produced embedded FW (Arduino) for rack mounted GPS signal distribution product (GPS Source IRMS).
Designed a RTG4 testbed with two sections. The first had designs for combinatoric, sequential, embedded RAM, PLL logic that was irradiated in a test chamber to find fail point. The second section was designed to operate above the failure threshold of the former section, and report failures in first section. This experiment determined the failure point of RTG4 for various operation.
2014-2018 Cobham Semi - ASIC/FPGA Design
Design and Verification of ARM M0+ Rad Hard Microcontroller. Designed Flash memory controllers (NAND and NOR). Wrote Firmware drivers in C. Ported Design to Altera FPGA for SW development platform. Leveraged same platform to build two Rad Chamber test controllers. Added required RTL, wrote drivers and control SW in C. Designed Rad Hard IC controller using Microsemi RTG4. This part interfaced with Rad Chamber test controller (described above), improving test capability 2010–2014 Digital Design Solutions - FPGA Design Engineer Designed RTL for cores used in US Army MET (Modernization of Enterprise Terminals) MilSatCom program. Cores were intended for multiple customers, synthesized to both Xilinx and Altera FPGA’s. Delivered an extensive, TLM based Verification environment for both individual block and system level as part of the program. This proved to be valuable when supporting IP among multiple customers who lack their own Hardware systems at this early point in the program.
Provided a second source solution, on request for a government agency, by developing a custom solution targeting a COT FPGA based acquisition board. This became the prime solution by accelerating design, API development and system integration to meet agency’s system test requirements. Accomplished by working closely with the OEM, and leveraging productivity tools such as MATLAB, System Generator and System Verilog, TLM verification. A 3-week lab debug schedule was met, and we immediately took the design into the ongoing system validation effort. This was completed on schedule, replacing the prime contractor’s solution, which couldn’t meet programs objectives.
Implemented FPGA based image-processing algorithms for an Airborne IR warning sensor system.
Delivered Fixed Point, Altera Stratix4 based RTL design using floating point C based model as both a reference (converted floating point models to real fixed-point hardware) and a verification source.
Delivered an improved, multiple protocol Demodulator, Modulator FPGA design based on a previous project for ICE V6M platform. In addition, I implemented a custom protocol Demodulator based on client’s algorithm, targeted to client’s proprietary FPGA platform. The algorithm was a series of MATLAB float point models describing carrier-phase reconstruction, channel equalization, AGC, adaptive equalization, demodulation, soft to hard level decision decoding, FEC. Converted the floating point to fixed point RTL, verified design and provided support thru system integration and testing phases. Modeled an Embedded processor (Dual Harvard, 20 bit Fixed point) using SystemC for DOD research lab.
Produced and supported the verification model used by multiple DOD contractors in their RTL designs. This also became the basis of an ISS (Instruction Set Simulator). Supported the final phase of the program by developing RTL model for hardware implementation, verified using the SystemC model along with System Verilog.
Delivered a multiple protocol Demodulator FPGA design, verification in 4.5 months as sole contributor. Project required a proprietary custom embedded processor, complex algorithms, DSP, multiple clock domains, Hyper Transport, PCIE, custom and commercial IP. I Utilized ICE V6M (Virtex6) SDR platform, System Verilog, VHDL, MATLAB, Linux, Perl, C++. I assisted system integration of this project by producing 80% of the Java code, relying on mentoring of skilled software colleagues.
Implemented and used Linux based design and verification system encompassing design rules, HDL tools, simulators, revision control (subversion) and documentation. Installed and managed this system on a network-based server.
2007- 20010 Embedded Systems Lab, Hewlett Packard, Senior Development Engineer Designed FPGA based IP using System Verilog, Synplicity for high availability HP servers. This included fabric, high-speed serial interfaces, power sequencing, motor control, noise cancellation, embedded processor support, etc. Assisting conversion of Altera based designs to ASIC for cost reduction.
Modeled and verified a high-performance Fabric Chip Set for high reliability HP servers using SystemC and C++. Specific duties were for PCIE Root Complex section. Author of DVCON paper “SystemC vs. System Verilog” and panelist for SystemC/C++ synthesis at NASCUG. Team Member of HP Corporate EDA and Methodology process group. 2002 - 2007 AMI Semiconductor Senior Staff Digital Designer, Team Lead Lead Engineer for a DSP embedded processor. This design was a pipelined, low power, 20-bit fixed point Dual Harvard embedded processor. The design was implemented in both an ASIC and an FPGA based emulation platform. Responsible for RTL implementation from architectural and conceptual drawings, architect of the processor specific SystemC/C++ based test bench. My direct contribution was the program control, pipeline, instruction decode, arithmetic unit, data path, logical unit, Verilog / SystemC co-simulation. The product can be seen as HYPERLINK "http://www.sounddesigntechnologies.com/products_Wolverine.php" \t "_blank" http://www.sounddesigntechnologies.com/products_Wolverine.php I was a Verification lead for a complex 1.4 million-gate multi-processor SOC and mixed signal CODEC. The SOC consisted of mixed signal and DSP units, proprietary wireless interface, our own embedded micro controller (see above), and wave digital filters. Our team developed DV procedures, coding standards, modeling and verification methods based on SystemC. This resulted in the sites first single pass ASIC tape out. I Assisted remote team with mixed signal ASIC that analyzes blood chemistry. Duties included algorithm modeling, RTL coding, verification. Continued support for this project modeling a PID mixed signal control loop using C++/ SystemC, and tied this into the RTL verification process.
Author of 4 SystemC based conference papers, including “Modeling Techniques with SystemC”, “Design and Verification of a Processor using SystemC, VHDL and Verilog” which was voted best design paper at DVCON 20004.
1999 – 2002 PalmChip Corporation, Staff HW Engineer, IP Development Manager, Architect
Designed highly configurable Ethernet, PCI block, DMA Interface, Memory Controllers
(SDR and DDR SDRAM, FLASH) cores. Integrated these into ARM7, ARM9 based SOC platforms for custom applications. These applications included Telecom, RAID, Disk Drive Controllers, Printers, and Medical Products.
As working manager of IP development group, Responsibilities include architecture, design, and verification of new IP, maintenance of legacy products. The group became a profit center with sales to external customers (Intel, TI, and LSI Logic). My key contribution was implementing DV standards and practices.
As Staff architect, duties include determining the next generation of PalmChip’s platform based Multi-Processor SOC architectures for Telecom (OC-48, 192), 3G wireless platforms. Work with established customers to improve performance of Palmchip first generation platforms. Also specify improvements, upgrades to legacy IP, as well as assist less experienced engineers with new designs. Act as a technical closer for sales. Presented paper titled “Configurable DMA Controller for an SOC” at DesignCon2000.
1997 - 1999 Cyrix Corporation, Senior HW/DV Engineer Design Verification for Integrated CPU/Graphics Product. This product combined a Pentium class processor, a 3D graphics processor, an SDRAM controller, PCI Bridge, and a 400 MHz Token Ring on one chip. I modeled a graphics/video mixer section of this chip using C++. This was used as a simulation and emulation model until a design could be implemented. I supported a processor companion chip, which included PCI, graphics, USB, keyboard interface, etc. This included investigation and resolution of field reported problems, release of design through foundry, and verification of final design. Device shipped in million units per month. 1995-1997 MYLEX Corporation, Senior HW Development Engineer Architected 200k gate ASIC, featuring dual 64 bit PCI interfaces, RAID 5 XOR Engine, 72 bit 100 MHz SDRAM interface. I Designed, implemented SDRAM interface featuring dual transfer controllers and ECC, performed Signal Integrity analysis using LINESIM, IBIS models. I Implemented an ASIC vendor selection process that was judged by all six vendors involved to be fair and objective.
Designed an interleaved FPM DRAM Controller for I960 Bus. Duties included selecting technology (ALTERA EPLDs), implementing a Verilog based test bench, modeling bus level interfaces, designing address and data control portion, writing test cases. Automated test bench utilizing TCL/TK and C programs. Designed, implemented a dual controller back plane containing 12 SCSI busses for COMDEX and customer reference. Collaborated on an Ethernet attached RAID product with SYMBIOS Ethernet Products Group
(Fort Collins). This resulted in a reference design using SYMBIOS 10BaseT chipset with an added PCI interface in place of proprietary switch bus, modifications to driver code.
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