Design Engineer Technologies Services
Resume:
RAJIVGANDHI. T
E-mail : **********@*****.***
Phone No: +1-425-***-****
Career Objective:
To associate with a progressive organization that gives scope to involve my knowledge and skills in, development, designing and testing of applications and be a part of a team that dynamically works towards the growth of the organization. Strong ability to produce results within a team environment or independently, utilizing a "take charge" attitude, self-motivation, and commitment. Total Years of Experience (as on date)
Overall experience after the educational curriculum is 14+ Yrs. Summary
Designing Time Critical Multilayer High Speed PCBs with high quality. Interaction with customer & PCB Manufacturer. Project Management, Strong Planning. In depth of working knowledge for High-Speed PCB designs, HDI, Flex, DFM and DFT, EMI/EMC consideration at PCB level. Holding work permit Visa (H1B): Valid up to Sep 30th, 2024 Passport no : V3566234
Experience:
Microsoft corporation, Redmond, Washington .
Designation : Senior Technical Lead Engineer.
Period : July 2022 to till date
Microsoft (Through HCL) Hyderabad.
Designation : Senior Technical Lead Engineer.
Period : Feb 2016 to till date
VVDN Technologies Ltd, BANGALORE.
Designation : Senior PCB Design Engineer.
Period : Nov 2014 to Nov 2015
L&T Technologies Services Ltd, CHENNAI.
Designation : Senior PCB Design Engineer.
Period : April 2008 to Sep 2014
Highlights
• 14+ years of experience in Multilayer High Speed Printed Circuit Board Layout Design.
• Expertise in High-Speed Routing & Length Matching like DDR2, DDR3, LP DDR4, PCI, PCIX, I2C, SATA, USB3, USB Type C, Thunderbolt etc.
• Expertise in Part Decal creation and Schematic symbol creation.
• Holding H1B visa & had one month training at MICROSOFT Campus in USA. Scholastic:
Bachelor of Engineering (ECE), 2007 passed out in Anna university. Page 2 of 7
Skill Set
Operating Systems Windows 2000/XP, Windows 10
Processors
Intel Atom, Avaton, Falcon valley, Free scale T4240, Power QUICC, Wintegra, OMAP, Briarwood.
Technologies Telecom, Networking, Video audio, consumer electronics Development tools
Cadence ALLEGRO Ver17x,Symphony Team design, Cadence-ORCAD, Capture CIS, System capture, PADS, PADS Logic, CAM 350 14.1, Blue print 6.1, View mate 10.6
Interface
PCI Bus, PCI-X, SATA, USB, XGMII, RGMII, SPI4, Ethernet 10/100/1000
& DDR I & DDR II, DDR III, DDRIV.
Design Expertise
DFM/DFT standards, Flex Design, EMI/EMC and SI requirements. Multiple split plane usage, Effective Blind, Buried Vias usage Board Types
Double layer, Multi-layer up to 24, Probe card up to 52 layers, RF design, Flex design single & muilti layer etc.
Roles and Responsibilities carried out
Project Name Multi-Function Communication Server Team Size 3 Duration 1 months
Role &
Contribution
To design the Printed Circuit Board with high quality services within the delivery commitments.
Responsible for the design aspects of the project.
Responsible for the maintenance and storage of the project documents.
Responsible for assisting the lead on enforcing quality guidelines
Post delivery activities like any support required for the customer after the layout package is released.
Synopsis
MFCS Comm Server cards are designed with Dual T4240processor from Freescale, and Dual AST1250 from A speed for Baseboard Management Control. The T4240 QorIQ multicore processor combines12 dual-threaded e6500 Power Architecture® processcores for a total of 24 threads with high- performance datapath acceleration logic and network and peripheral bus interfaces required for networking, telecom/datacom, data center, wireless infrastructure and mil/aerospace applications.
Technologies
T4240– Freescale Microprocessor
6 DDR3 DIMM module
512MB NOR flash
20 Layer Board
Tools Cadence allegro 17.4 and Cadence Orcad Capture Page 3 of 7
Project Name
Multi-Function Communication Server
with Scale-out
Team Size 2
Duration 1 Months
Role &
Contribution
To design the Printed Circuit Board with high quality services within the delivery commitments.
Impedance controlled stack-up used
Applied critical DFM constraint rules
Digital & Analog mixed layout design placement
HDI design techniques – used blind & buried vias
ICT test point coverage - 92%
Design rules checks (DRC) – Validation
Released Gerber file/ODB++ to fabrication and assembly house.
Post delivery activities like any support required for the customer after the layout package is released.
Synopsis
A Dual T4240 based Communication server with Scale-out option, offering a Powerful unified communication solution with up to 80G of external network connectivity, SRIO inter-chip and external connectivity. External SRIO interface helps to (scale-out) expand system
With similar system through External SRIO switch.
Tools Cadence Allegro 17.4, Orcad schematic capture Project Name Data Center Storage Server Team Size 2 Duration 1 months
Role &
Contribution
To design the Printed Circuit Board with high quality services within the delivery commitments.
Feasibility study on routing to contain within number of layers.
Responsible for the design aspects of the project.
Responsible for the maintenance and storage of the project documents.
Responsible for assisting the lead on enforcing quality guidelines
Involved in Complete Layout Design.
Synopsis
A Dual T4240 based Data center Storage appliance, offering a powerful unified communication solution with up to 80G of external network connectivity, SRIO inter-chip connectivity and multiple SATA HDD’s and PCIe based SSD’s. The storage appliance is designed to provide features that include data compression, de-duplication and encryption. The use case is Storage Virtualization as a Software Defined Storage (SDS) appliance Technologies
The board has 20 layer stack-up with 2.5mm thickness.
It has 1680 components, 4947pins & 5217 nets.
T4240– Freescale Microprocessor
6 DDR3 DIMM module
PCI-Express (32Gbps)
I2C EEPROM for Configuration
89HT0808P - PCIe Signal Retimer from IDT
Maximum number of pins in single IC is 783
The minimum drill size used in the board is 10mils
Final Gerber delivered for manufacturing
Tools Cadence Allegro 17.4, Orcad schematic capture Page 4 of 7
Project Name GE UCSA card Team Size 2
Duration 3 months
Role &
Contribution
To design the Printed Circuit Board with high quality services within the delivery commitments.
Responsible for the design aspects of the project.
Achieved 100% test point requirement for all the signal nets in the board.
Interacting with customer for project reviews and status meetings.
Responsible for the maintenance and storage of the project documents.
Responsible for assisting the lead on enforcing quality guidelines
Post delivery activities like any support required for the customer after the layout package is released.
Synopsis
The Intel Tolapai & Altera’s Cyclone II - EP2CS50 FPGA based core compute engine is targeted for use in the High-speed network. Board is designed with major components involves Intel’s Tolapai,Altera FPGA, DDRII 64bit driving at 600Mhz, PCI X,SATA connector, 1088 pin BGA, Compact flash
,Oscillators,PMC slots etc.
Technologies
Intel - Tolapai - EP80579
Altera FPGA - Cyclone II - EP2CS50
Broadcom PHY
DDRII,64bit @ 600Mhz
Compact flash
PCIE & SATA
RGMI and USB (1G Ethernet ports)
PCI bus
SATA bus
Tools Cadence Allegro-17.4, Orcad schematic capture Project Name
CPU Mother Board Using Intel
processor
Team Size 4
Duration 4 months
Role &
Contribution
Project planning, splitting the design to multiple designers to achieve the schedule
Status update to customer on daily basis, have conference call whenever required.
Ensure all the Engineering feedbacks are implemented in Layout design.
Enforcing process adherence in the project execution & meeting delivery deadlines.
Approval of design at each phases before getting customer approval Synopsis Desktop Mother board designed for Intel
Challenges,
Technologies
used
The board has a 06 layer stack-up with 62 mils thickness.
It has 294 components, 3015 pins & 2354 nets.
It includes DDR, FSB, SATA-II, EMI, PCI-X, PCI-EX, CPU, PCH Interface etc.
One GND plane and One split power planes used.
Page 5 of 7
The minimum pitch across pins being 31.7493 with a trace width of 5mils and air gap of 4mils.
It has multiple power supplies with different types of power rating. Tools Cadence Allegro 17.4, Orcad schematic capture Project Name GW2820TX PROTO-BOARD Team Size 3
Duration 2 months
Role &
Contribution
Project inputs study
Project planning
Meeting day-day task and interaction with customer to meet the same
Create / Maintain Discussion log
Sending day wise status /queries and tracks the same. Synopsis
The GW2820TX Proto-board is intended to demonstrate up to 2.5 GB/s bandwidth for HDMI gateway system over Fiber Optic cabling. Challenges,
Technologies
used
The board has a 6 layer stack-up with 62 mils thickness.
It includes SPI Interface, Transceiver / Fiber optic interface, Clock oscillators, etc.
It has HDMI Receiver and Transmitter.
It has Video and Audio interface.
Signal integrity, Thermal analysis, DFM and DFT requirements. Tools Cadence allegro17.4 & Orcad Capture CIS
Project Name FPGA EMULATION BOARD Team Size 2
Duration 3 months
Role &
Contribution
Projects analyze requirement verification.
Project planning, splitting the design to multiple designers to achieve the schedule
Status update to customer on daily basis, have conference call whenever required.
Ensure the DFM, DFT is met on the design.
Ensure all the Engineering feedbacks are implemented in Layout design.
Synopsis
FPGA emulation board is used to compress the audio and video signal by using SPARTAN 3A DSP FPGA.
Challenges,
Technologies
used
The board has a 6 layer stack-up with 62 mils thickness.
It has 849 components, 3498 pins & 2623 nets.
It includes SPARTAN 3A DSP FPGA for Encoding & compression processing, Ethernet controller, DDR SDRAM, Flash memory, JTAG, RS232, video DAC etc.
Maximum number of pins in single IC is 484.
The minimum pitch across pins being 31.49 with a trace width of 4mils and air gap of 4mils.
The minimum drill size used in the board is 10 mils.
Board size used 6” x 4”.
Tools Cadence allegro17.4 & Orcad Capture CIS
Page 6 of 7
Project Name 4GPLx859_Tera Probe_LTCC Team Size 3
Duration 3 months
Role &
Contribution
Projects analyze requirement verification.
Project planning, splitting the design to multiple designers to achieve the schedule
Status update to customer on daily basis, have conference call whenever required.
Ensure the DFM, DFT is met on the design.
Ensure all the Engineering feedbacks are implemented in Layout design.
Synopsis
Low Temperature Co-fired ceramic design (LTCC) Pogo and MEMS design using Blind and buried via concept. Adapt knowledge of Net list creation, EDA cad work and up to end of CAM work. LTCC - Low Temperature Co- fired Ceramics design is the interconnection of POGO and MEMS side patterns LTCC technology involves the production of multilayer circuits from ceramic substrate tapes or sheets
Challenges,
Technologies
used
The board has 38 layer stack-up with 7.5mm thickness.
HDI Technology.
It includes 859 MEMS and POGO.
Routed using different topology with maintaining the layer rules.
Identifying the same blocks and arraying.
Padstack checking.
100% stitching vias provided for power nets.
GND hatching provided layer by layer.
Tools Cadence allegro17.4
Project Name Probe Card design Team Size 5
Duration 1 months
Role &
Contribution
Projects analyze requirement verification.
Project planning, splitting the design to multiple designers to achieve the schedule
Status updates to customer on daily basis, have conference call whenever required.
Ensure the DFM, DFT is met on the design.
Ensure all the Engineering feedbacks are implemented in Layout design.
Synopsis
Probe card is an interface between an electronic test system & a semiconductor wafer. It provides an electrical path between the test system and the circuits on the wafer, thereby permitting the testing and validation of the circuits at the wafer level, usually before they are diced and packaged.
Page 7 of 7
Challenges,
Technologies
used
The board has DUTs interconnected with relays & tester connectors with MEMS technology.
It has a 54 layer stack-up with 250mil thickness.
Design has 17192 pins, 1259 components & 6320 nets.
Minimum pitch in the design is 30mils with trace width of 5mils and air gap of 5mils.
Unique Length Matching across board.
Minimum drill size used in the board is 10mils with DFM requirements met.
Tools Cadence allegro17.4
PERSONAL DETAILS
Date of Birth : 04-12-1984
Gender : Male
Marital status : Married
Present Address : 15233 NE 15th PL, Bellevue, WA
Languages Known : English, Telugu, Tamil, and Kannada. Email ID : **********@*****.***
Declaration:
I hereby state all the above details are factual to the best of my knowledge. Place: Bellevue
Date: 08-30-2022 (RAJIV GANDHI.T)
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