Arturo Scotto

Analog Mixed Signal Design Engineer

Enthusiastic Analog Mixed signal engineer, with 10+ years of experience and a patent granted

(Differential amplifier that compensates for process variation) eager to contribute to team success through hard work, attention to detail and excellent organizational skills. Clear understanding of Electronics (analog/digital) and training in System on Chip design. Motivated to learn, grow and excel in silicon industry

Work History

To date -

2021-12

2017-02 -

2020-04

System Analyst (consultant)

Tony s BBQ franchise, Houston, Texas

• Analysis and standardization of franchise

procedures and image.

• Analysis and processing of information to create a franchisee s manual

• Analysis and processing of information to create an operation manual

• Analysis and processing of information to create an image manual

• Present and communicate results, advances, and

documentation

• Organization of the workshop for franchisees for standardization and applying changes

Analog Mixed Signal Design Engineer

WIPRO, Guadalajara, Jalisco

• Supported engineering design development

through analysis, simulation, test and validation.

• Work for NXP SerDes Team on custom blocks design: Transmitter Receiver, Frequency divider, Idle Detect, Clock Driver, Clock Distribution Net, Crack Detect

• Verify designs for Safety Area Operation (SOA),

Electromigration, LVS, DRC, DFM, functionality, IR drop.

Contact

Address

14418 sweetwater dr

baytown Texas 77523

Phone

+52-331-***-****

+1-832-***-****

E-mail

adsoa2@r.postjobfree.com

Skills

Analog electronics

design

Excellent

Expert in schematic

design

Excellent

Fundamental engineering

concepts

Excellent

C/C++

Very Good

• Design test benches for DUT (Design under test) to meet specs

• Layout implementation for custom blocks like

Transmitter(TX), frequency divider, Clock Net

• Work for Intel SoC team on Physical design task like Synthesis,

P&R, floor planning

• Delivery Manager for IES (Industrial Engineering Solutions) since 2019 responsible to coordinate

engineering VLSI(16 members) and Embedded

programming (40 members) teams

2012-04 -

2016-06

Analog Design Engineer (Power Integrity)

Intel, Guadalajara, Jalisco

• Design power integrity solutions, use tools and

analyses to identify root cause and corrective

actions to technical challenges.

• Drove design improvements which resulted in

savings and improved profit margins and over all

power integrity.

• Create Models (S-parameters, RC and RLC) of

power routes and planes for Mother Boards, DDR4

Memory, packages, Voltage regulators, chip

current consumption profiles and coils

• Create test benches for all power system including all path from Voltage regulator, Mother board,

package, memory and chip as well as power

integrity for new memory technology

• Resolved problems, improved design on cross

functional multicultural teams provided exceptional service to ensure power integrity.

• Used critical thinking to break down problems,

evaluate solutions and make decisions.

Cadence (Virtuoso,

Analog Artist,

Very Good

Mixed signal

Very Good

SPICE

Very Good

ASIC Layout

Very Good

Simulation

Very Good

Verilog

Good

Place & route

Average

2007-10 -

2012-03

Analog Design Engineer

Freescale, Guadalajara, Jalisco

• Supported engineering design development

through analysis, simulation, test and validation.

• Worked on leading-edge technology nodes to build elite custom analog designs for SerDes IP.

• Worked on several High speed serdes IP blocks

Backend activities like DRC cleaning, LVS checks,

timing cleaning (STA), generation on SPEF for

parasitic elements in layout, incremental SDF (noise analysis), SDF for digital simulations,

• Test validation for serdes IP performing activities like production test, functional verification both with verilog comportamental models and gate level

netlists and LEC (logic equivalence compare)

• Patent granted US 8035448 differential Amplifier that compensates for process variations

Education

2006-02 -

2007-04

Specialization: System On Chip Design

ITESO - Tlaquepaque Jal

• Received CONACYT Scholarship

• Note 90/100

1998-07 -

2003-07

Bachelor of Science: Computer Science

And Programming

ULSAB - Celaya Guanajuato

• Note 90/100

Languages

Spanish native

Excellent

English advanced

Very Good

Contact this candidate