Processor Lecturer
Resume:
Phone
************@*****.***
Education
Master of Engineering - VLSI Design 2010
Anna University, Coimbatore
Bachelor of Engineering - Electronics & Communication 2005 Dr. MCET, Pollachi
SUMMARY
Enthusiastic to become Design
verification engineer eager to
contribute to team success
through hard work, attention to
detail in coding and excellent
organizational skills. Motivated
to learn, grow and excel in VLSI
industry
Work Experience
Assistant Professor 01/2011 to 06/2016
SRM University Chennai
Lecturer 06/2007 – 04/2010
Amrita Vishwa Vidyapeetham University Coimbatore
Meena Parthasarathi
Skills
HDL languages: Verilog, VHDL
HVL languages: System Verilog
EDA Tool: Model Sim, Xilinx – ISE, Quartus prime
Programming Languages: C, core Java
Operating System: Linux, Windows
Scripting Language: Perl
Accomplishments
Advanced ASIC verification course at MAVEN SILICON Papers Published:
A new decoding algorithm for extended turbo product codes without fetching error patterns at Vidya academy of science and technology. Projects:
Optimized Hardware processor for elliptic curve cryptography. It is to exchange private information over public mediums with data protection against unauthorized access with ECC. The ECC computation is a scalar multiplication, translating into an appropriate sequence of point operations, each involving several modular arithmetic operations implemented using ModelSim and FPGA kit
Noise Reduction and Echo cancellation: It is the process of reducing unwanted noise and echo in the speech signals which improves the quality of speech and performance of the system using matlab
Router Design. It is a networking device that forwards data-packets between computer networks which includes Register, FIFO, FSM, and Synchronizer are simulated using ModelSim, synthesized using Quartus prime 17.1 and connected with the top module
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