Validation Engineer Systems Group

Anant Mathur

***** ** **** **** ** BEAVERTON OR *7006 Cell: 484-***-****, E-mail: **************@*****.*** Objective

To obtain a full-time position as FPGA based design and Validation Engineer Work Experience (July’2016- present)

Communication Engineer II, Electric Boat, General dynamics, Groton, CT: November 2017-sep 2020

● As a member of the Combat Weapons Systems group, I Quartus tools for board and FPGA design. Developed RTL (VHDL) code for UART-USB, SPI-UART HW level communication IPs. Optimized OPAMP based power delivery circuits.

● I used TEAMCENTER for component analysis for System Engineering and Technical documentation for the project.

● Board level troubleshooting and tests on a regular basis. Software Engineer: SAI Technologies, Santa Clara, CA : July 2016-Oct'2017

• Developed Cyber Intelligent Security Software Interceptor, using LDAP server to provide Threat Centric IAM approach

• Integrated Antispam packet filtering with Cyber Forza

• Implemented DDOS (Distributed Denial Of Service) algorithms in Perl/Python and its test environment in FreeBSD

• Developed technical documents like reference manual, users guide, application guide for the Security Software products

• System validation of customized network Switch and Cyber Security Software product Education

The Pennsylvania State University Graduated 2015

Bachelor of Science in Computer Engineering

Minoring in Engineering Leadership Development

.

Additional Engineering Experience

VLSI Layout design:

● Using the Virtuoso tool, I have designed a chip using cell design, place & route, parameter extraction, and spice simulation of a digital circuit. I created basic cell structures (Inverter, Adder etc.) in Magic on Ubuntu platform and performed SPICE simulation to verify the design. Skills

C++ JAVA SolidWorks AutoCAD

Quartus Qtsim MAGIC VHDL

Visual Studio Cadence Virtuoso RTL C

Status

U.S. Citizen

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