NIVETHA.K

***-**, ********* ***** ******,

Vellakkalpatti (PO), Rasipuram(TK),

Namakkal (DT), Tamil Nadu, India.

Pin: 637406.

Mobile : +91-978*******

Email Id : adpmo7@r.postjobfree.com

CAREER OBJECTIVE

Through facing the real-world problem and challenging environment that encourage continuous learning and creativities to explore skills and talents in an organization that offers growth while being resourceful and innovative in the position of effective developer.

TECHNICAL SKILLS

Good understanding in Static Timing Analysis and Design rule checks.

Basic knowledge in Digital design, Verilog coding and Low power VLSI techniques.

Basic knowledge in Cadence Encounter Tool.

Comprehensive knowledge of Physical Design implementation, Physical Design strategies-Sanity checks, Floor Planning, Power Planning, Placement, CTS and Routing.

EXPERIENCE

Internship in VLSI Physical Design at QSoCs VLSI Training Institute.[July2017- Jan 2018]

PROJECT in QSOCs Pvt Ltd Bangalore

Project-I: Block level

Description:

Understanding the Physical Design flow from Floor planning to Routing and Understand the different issues during flow like Congestion, Timing Issues (Setup and Hold violations), DRC violations and applied different Techniques to Fix them

Project Title

Leon Processor Tools : Cadence ENCOUNTER

Role

PnR

Technology node

45nm TSMC

Gates Count

35 K

Macros

4

Clocks

2

Frequency

125MHz

Metal Layer

9

Project-II: Block level

Description:

Understanding the PD flow concepts and implementing them which include Sanity checks, Floor Planning, Power planning, Placement, CTS & Routing.

Project Title

Cadence ENCOUNTER

Role

PnR

Technology node

28nm TSMC

Instances Count

18 K

Macros

1

Clocks

3

Frequency

774.6MHz

Metal Layer

8

Project-III: Chip level

Description:

Understanding the PD flow concepts and implementing them which include Sanity checks, Floor Planning, Power planning, Placement, CTS & Routing.

Project Title

DTMF_CHIP Tools : Cadence ENCOUNTER

Role

PnR

Technology node

90nm TSMC

Instances Count

5 K

Macros

4

Clocks

2

Frequency

140MHz

Metal Layer

6

EDUCATION QUALIFICATION

Course

Institution

Board/

University

Year of completion

M.E.

(VLSI DESIGN)

Sri Sairam Engineering College, Chennai.

Anna University Chennai.

2017

B.E.

(ECE)

Sri Sairam Engineering College, Chennai.

Anna University Chennai.

2014

Diploma

(ECE)

Muthayammal Polytechnic College, Namakkal.

State Board.

2011

H.S.C

Kalaimagal Metric Higher Secondary School

State Board of Tamil Nadu, Namakkal.

2009

S.S.L.C

Government Girls Higher

Secondary School

State Board of Tamil Nadu, Namakkal.

2007

ACADEMIC PROJECT

SELF SCHEDULED PERFORMANCE MONITORING OF DISTRIBUTED

SOLAR PANEL USING IEEE 802.15.4 USING MAC PROTOCOL

Duration : 6 Months

HIGH SPEED 16-BIT VEDIC MULTIPLIER

Duration: 1Year.

EXTRA-CURRICULAR ACTIVITIES/ ACHIVEMENTS

Topper in post graduate (PG).

NSS volunteer and actively participated in seven days camp held at Vadugam Village.

Won best outgoing student award.

INDUSTRIAL EXPOSURE

Attended one day workshop on “Science of EMI”, in Sri Sairam Engineering College, West Tambaram, Chennai-44.

DECLARATION

I hereby declared that the above mentioned information’s are truly to the best of my knowledge.

Place : Bangalore

Date : 11-02-2018 YOURS TRULY

[NIVETHA.K]

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