JAYABHARATH P

adodvq@r.postjobfree.com

894*******

Address: ***/* ******** ***** ******

Chennampet, vaniyambadi

Tirupattur(DT),Tamil nadu-635751

CAREER OBJECTIVE

To make a career that offers challenge

which requires new efficient solutions and

growth with opportunities to enrich my

knowledge and skills.

AREA OF INTEREST

Physical design and DFT...

Digital CMOS design

Electronic devices and circuits

Digital signal processing.

PROJECT WORK

Implementation of Matrix Vector

Multiplication in LSTM network using

Distributive Arithmetic in Xilinx ISE

Implementation of half precision mantissa

multiplier using FMA in xilinx

SKILLS

Hands on experience in

vivado, cadence,

labview,quatrus, Xilinx.

proficient in Verilog,c++

LAYOUTS AND SYNTHESISED

PROJECTS

Design of finite state machine, registers, counters Matrix vector multiplication in lstm using DA

Half precision multiplier using FMA

EDUCATION

M.E-VLSI DESIGN/2021

Government college of technology

coimbatore

CGPA-7.1

B.E-ECE/2018

Thanthai Periyar Government Institute of

technology vellore

CGPA-6.66

HSC/2014

Indian Matric Hr Sec School harur

Percentage – 91.50%

SSLC/2012

ST. Pauls Matric Hr. Sec School vaniyambadi

Percentage – 92%

CO-CURRICULAR AND EXTRA-CURRICULAR ACTIVITIES

Participated in the R and D trends workshop, learned Verilog module, NI- labview tool.

Participated in the Novel 5g and OFDM development workshop. WORK EXPERIENCE

I had an working experience of 1 year as an R and D engineer in circuit design and developing of USB charger at Multilink India pvt ltd-Bangalore.

.