Satya Sudhakar Y

email: admxxz@r.postjobfree.com

Mobile: 91-984*******

Saturday 5th June, 2021

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First Name Satya

Middle Name Sudhakar

Surname Yedlapalli

Date of Birth 26th April 1972

Qualification PhD in Signal Processing from the E.C.E Dept., Indian Institute of Science(I.I.Sc), Bangalore. Web Profile http://www.researchgate.net/profile/Satya-Yedlapalli/ Areas of Interest Digital Signal Processing Algorithms, DSP/ASIC based embedded systems (Communication Systems, Radar Systems, Bio-Medical Systems etc.) and Data Analytics. 2 Development Projects

Manage/Mentor projects which require atleast one of the following

• Technical expertise for innovative and cost-effective system solutions.

• System Level Simulation, modeling and performance optimization with novel algorithms and architectures.

• Numerical Optimization and Implementation of fixed point algorithms on DSPs/ASICs/SoCs. 3 Experience(Industry : 20 years, Academic : 8+ years) 01Aug2014 - Date: [2491days+] Associate Professor, Work Integrated Learning Program(WILP) at BITS- Pilani, Off-Campus Center, Bangalore,

01Mar2013 - 31July2014: [517days] Principal Engineer & Technical Mentor(DSP Systems), Aureole Technolo- gies(Pvt.) Ltd., (AUT), Bangalore

12May2011 - 28Feb2013: [659days] Principal Engineer, SaankhyaLabs Pvt. Ltd.(SKYL), Bangalore. 01Jul2010 - 14Apr2011: [288days] Sr. Chief Engineer(System Architect) in the R & D unit of Samsung India Software Operations Pvt. Ltd.(SISO), Bangalore.

01Apr2010 - 30Jun2010: [91days] R & D Advisor and Technical Manager, Aureole Technologies(Pvt.) Ltd.,

(AUT), Bangalore

01Dec2009 - 31Mar2010: [121days] Research Associate in Statistical Signal Processing Lab (SSPL), E.C.E Dept., I.I.Sc, Bangalore

28Dec2001 - 26Oct2006: [1764days] Lead Engineer at Texas Instruments India Pvt. Ltd.(TI), Bangalore. 11Jan1996 - 26Dec2001: [2177days] Lead Engineer at Motorola India Electronics Pvt. Ltd. (MIEL), Bangalore. 1

01Mar1993 - 10Jan1996: [1046days] Research Engineer at Centre for Development of Telematics(CDOT), Ban- galore.

PhD-tenure Aug-2004 to Jan-2010 at I.I.Sc, Bangalore. Oct-2006 to Jan-2010: as a Regular Research Scholar with I.I.Sc scholarship. Aug-2004 to Oct-2006: as an External Registration Research Scholar(ERP-PHD) from Texas Instruments. 4 Summary of Projects Handled

• Optimization of core DSP algorithms and System architectures;

• Beamforming Algorithms, Novel ECG Compression Algorithms;

• Adaptive Filters, Vector-Space Methods, Spectral Estimation;

• Digital Signal Processing Algorithms (FFT, DCT, MDCT etc.), Multirate Filter Banks, some algorithms in Speech Coders;

• Fading Channel Simulators, Cross Talk effects, Digital portions of DSL Modems(Annex-C), OFDM in WLAN;

• Some Core Algorithms in Modems(V-Series), Error Control Codes, Adaptive Echo Cancelers and Equalizers 5 Projects Handled

W1: AUT: Development of optimized Fixed point signal processing algorithms (i) for narrow band FIR filters

(ii) vector-space methods for communication systems (iii) lattice structures (iv) Iterative Numerical Matrix Methods

W2: Systems and Algorithms Group(Saankhya Labs:Coding and fixed point implementation handled by different teams)

• Matrix Algorithms: Review and Analysis of some of the key Matrix Algorithms required for Wireless Communications.

• Group Delay Equalizer: Group Delay Compensation filter for ATV standard.

• Receiver Chain: SQNR Optimization of front end signal processing chain across all TV standards.

• Novel Least-Square FIR Filter Design: Optimization of all linear-phase filters across all the TV stan- dards. This is based on non-equiripple design.

• Lattice Structures for Linear Phase FIR filters(LP-FIR): Defined the architectures for the lattice struc- tures [Conf. article C2]. Analysed their impact w.r.t the system performance, SQNR.

• Architecture for a 2

15

-point FFT: Proposed an optimized version of radix-2 τ

family of FFTs for DVB-T

systems. Analysed its impact w.r.t to the system metrics and proposed the novel architectural require- ments.

• Other Key Algorithms: Fast convolution for real LP-FIR filters and related architectural design. Some novel FIR filter designs which are optimized for both SQNR and order. W3: Advanced Technology Group(Samsung India Software Operations: Technical Project Lead/Mentor)

• Bio-Informatics: Devised a novel algorithm for ECG Compression for portable ECG monitoring devices.

• System Simulation: Managed a team responsible for System Level Simulation of a communication sys- tem for low power Body Area Networks.

2-8

• Algorithms: Delivered a series of tutorials on Linear Algebra to a team responsible for developing real time algorithms in wireless communications.

W4: IISc, SSP-Lab: This research work was focussed on some optimal implementation aspects of most frequently used signal processing algorithms in communication systems. W5: Wireless LAN(1EEE802.11g)-System Performance Validation(Texas Instruments:)

• OFDM SQNR Optimization Proposed a unified architecture for existing Radix-2 2

and a new Radix-

2

3

FFTs for OFDM demodulation. This implements both the 128-point FFT in Radix-2 2

and 256-point

FFT in Radix-2

3

.

• Novel Fixed Point Scaling Identified a novel fixed point scaling algorithm which achieves an optimum SQNR independent of the Peak-to-Average Ratio of the OFDM Signal. A TI-Patent is approved for filing. W6: DSL System(Texas Instruments:)

• The DSL-System Performance tuning aspects of the existing CPEs/COs. This includes system simula- tions(Matlab), validation and testing strategies.

• Design of Transmit IIR Filter, Simulation with Annex-C Channel Noise Models, Terminal TCM-ISDN Clock Recovery-TTR, Some Power Management Functions for ADSL2 W7: Projects at Motorola India:

• G.721 and G.168 Echo Canceler on DSP568xx with Integrated Matlab Test Setup.

• Voice Pager based on InFLEXion and REFLEX protocols on DSP568xx.

• Forward Error Correction Codes(Reed-Solomon and Bose-Chaudhuri-Hocquenghem) design for Third Generation Cellular System.

• Some modules for Variable and Low Bit Rate Speech Coding technology

• Integrated Despatch Network(iDEN) Channel Simulator modeling in Matlab.

• Trellis Coded Modulation in V.32, V.34 modems.

• Convolution encoder and Viterbi Decoder (VD) for V.32 modem on DSP568xx. W8: Projects at CDOT:

• Multipath Fading Simulator Model and Adaptive Blind Equalizers(C Language).

• Adaptive Echo Canceler for C-DOT Very Small Aperture Terminal (VSAT). 6 Patents

PT1: Title Determining Spectral Samples of a Finite Length Sequence at Non-Uniformly Spaced Fre- quencies

Details Patent No. US8594167B2, Granted on 26-Nov-2013 Inventors Satya Sudhakar Yedlapalli and K. V. S. Hari PT2: Title Filtering Discrete Time Signals using a Notch Filter Details Patent No. US9112479B2, Granted on 18-Aug-2015 Inventors Satya Sudhakar Yedlapalli and K. V. S. Hari PT3: Title Fixed Point Scaling for radix-2

2

and radix-2

3

Fast Fourier Transforms for Optimal Signal to

Quantization Noise Ratio(SQNR).

Details Approved on March 28, 2006 by Texas Instruments Inc. Dallas DSP Cores Patent Committee Docket Number:TI-61693.

Inventor Satya Sudhakar Yedlapalli.

3-8

PT4: Title Application of Barker Codes and a Class of Pseudo Random Sequences, for a Correlation Based Time Domain Reflectometry Technique in Wireline DSL Single-Ended Loop Tests (SELT) Details The U.S Patent Publication number: US 2005/0083860 A1, Filing date: 15 Oct 2003. Inventors Sankaranarayanan Ravishankar and Satya Sudhakar Yedlapalli. 7 Research Work at I.I.Sc(PhD)

The Line Spectral Frequency model of a finite length sequence and its applications:

• The Line Spectral Frequency(LSF) of a causal finite length sequence is basically a frequency at which the spectrum of the sequence annihilates or the magnitude spectrum has a spectral null. A finite length sequence with (L + 1) samples having exactly L-LSFs is referred as an Annihilating(AH) sequence. In 1975 Fumitada Itakura showed that a real minimum-phase sequence can be expressed in terms of LSFs. Peter Kabal and Ramachandran in 1986 gave a working algorithm which lives in every speech coder/mobile-phone today. The article [J2] presents a more precise and an efficient algorithm to compute these LSFs using some spectral properties of sequences (1/3rd the computational cost of Kabal and Ramachandran’s algorithm).

• The concept of LSFs is extended to any arbitrary sequence. This framework develops an LSF model of a causal finite length sequence with an arbitrary choice of model parameters(arbitrary phase shift and integer delays). An LSF model basically consists of a set of LSFs, complex gains and a procedure/structure to synthesize a sequence or to compute its spectrum. Consequently, a given sequence can be represented by many LSF models each defined by a set of model parameters. The LSF models are also robust for fixed point signal processing operations as they are real and signed fractions. With this novel extension, the LSFs can be used to represent any complex sequence in an efficient format which is amenable to many signal processing operations both in time and frequency domains. The LSF model being a fundamental representation framework of any finite length sequence has potential applications in the areas of broad-band communications, cognitive radio(spectral sensing), array signal processing, filtering and spectral estimation.

• Key-Result-1:(Time domain application) The LSF model of a sequence is used to obtain a novel canonic filter(FIR/IIR) structure.

• Key-Result-2:(Frequency domain application) A novel NuFFT(non-Uniform Fast Fourier Transform) algo- rithm is presented which uses the LSF model of the sequence for DTFT sampling. The NuFFT is efficient as it uses the non-uniform sampling of the characteristic AH-sequences defined by the LSFs within the LSF model. The efficacy of this NuFFT is more pronounced for sparse and more precise spectral sampling.

• This work also gives insight into some novel properties of LSFs, which can be exploited by many signal processing systems.

8 Journal Publications

J1: Title The line spectral frequency model of a finite length sequence Author S. S. Yedlapalli and K. V. S. Hari

Publisher IEEE Journal of Selected Topics in Signal Processing - Special Issue on Model Order Selection in Signal Processing Systems - June 2010

J2: Title Transforming Linear Prediction Coefficients to Line Spectral Representations with a real FFT Author S. S. Yedlapalli

Publisher IEEE Transactions on Speech and Audio Processing, 13-Sept 2005. 4-8

9 Conference Publications

C1: Title On the Modeling of Low Pass Characteristics of Super-Regenerative Receiver for High Speed Sim- ulation

Authors Chakraborty, T.S; Yedlapalli, S.S.; Naniyat, A.; Young-Jun Hong; Sungjin Kim Publisher Vehicular Technology Conference (VTC Fall), IEEE, Samsung India Software Operations(SISO), Bangalore, 5-8 Sept. 2011.

C2: Title A novel property of an Auto-Correlation Sequence and some Applications Authors Satya Sudhakar Y and K. V. S. Hari

Publisher International Conference on Signal Processing and Communications(SPCOM2010), Indian Institute Of Science(I.I.Sc), Bangalore, July 18-21, 2010.

C3: Title The canonic Linear-Phase Fir Lattice Structures Authors Satya Sudhakar Y and K. V. S. Hari

Publisher National Conference on Communications(NCC2010), Indian Institute of Technology(I.I.T), Madras, Jan 29-31, 2010.

C4: Title An Overview of PM1 algorithm for efficient computation of real data DFT on Digital Signal Pro- cessors and its implementation on Motorola DSP566xx for real and complex data. Authors Satya Sudhakar Y and Harsha Deep Gadi

Publisher The International Conference on Signal Processing Applications & Technology (ICSPAT), Nov 1-4, 1999, held in Orlando, Florida, U.S.A. This was recognized as the best paper for the application area of Efficient Algorithms

10 Courses Taught

1. Digital Signal Processing, Advanced Digital Signal Processing

[WILP, M.Tech-Embedded Systems of BITS-Pilani University, 4-Semesters]; 2. Advanced Control Systems

[WILP, M.Tech-Embedded Systems of BITS-Pilani University, 2-Semesters]; 3. Fault Tolerant System Design

[WILP, M.Tech-Embedded Systems of BITS-Pilani University, 4-Semesters]; 4. Advanced Statistical Techniques for Data Analytics

[WILP, M.Tech-Embedded Systems of BITS-Pilani University, 2-Semesters]; 5. Quantitative Methods

[WILP, M.B.A of BITS-Pilani University, 1-Semester]; 6. Computer Programming in MATLAB

[WILP, B.Tech Core course of BITS-Pilani University, 9-Semsters]; 7. Architecting a Computational Model in MATLAB

[For startups in the domain of DSP, Communication]; 8. LATEX based Technical Documentation and its application for managing Large Simulations & validation of Embedded Systems.

[To several clients on behalf of Aureole Technologies Pvt. Ltd. Bangalore Apr2014-July2014]; 9. LATEX based Technical Report Writing

[IEEE Workshop at ECE Dept., I.I.Sc, Bangalore June2013]; 5-8

10. A Short term course on Linear Algebra

[To a client on behalf of Aureole Technologies Pvt. Ltd. Bangalore Jan2014-June2014]; 11. A Short term course on Spectral Estimation Techniques

[To a client on behalf of Aureole Technologies Pvt. Ltd. Bangalore Jan2014-June2014]; 12. Visiting faculty at S.J.C.I.T, Chickballapur(Bangalore), for Linear Algebra

[1st semester M.Tech-E.C.E of Visvesvaraya Technological University, Aug2013-Dec2013]; 13. Visiting faculty at ATRIA Institute of Technology, Bangalore for DSP-Architectures

[7th semester B.E-E.C.E of Visvesvaraya Technological University, Jul2009-Dec2009]; 14. Full term courses at I.E.T.E, Bangalore (i) Signals and Systems (ii) Analog Communication Systems (iii) Digital Signal Processing June2006-Dec2006;

15. Short term courses (1993 - 2005) at I.E.T.E, Bangalore (i) Digital Signal Processing, (ii) Analog Communi- cations Systems, (iii) Multi-Rate Digital Signal Processing; (iv) Spectral Analysis and estimation; 16. Presented a full day session on usage of the LATEX package in ”Two-day workshop on Research Methodologies and Technical Writing Skills”

[Visvesvaraya Technological University, Oct-2013]; 17. Series of Lectures on some selected topics in Linear Algebra to help the R & D team in Wireless Communi- cations at Samsung India Software Operations and Saankhya Labs. 11 My Theses

1. Title The Line Spectral Frequency model of a finite length sequence and its applications. Details For PhD (Advisor: Prof. K. V. S. Hari, I. I. Sc); Completed in Apr-2009 2. Title Study of Fractionally Spaced Adaptive Equalizer for a channel with Multipath distortion. Details For M.Tech (Advisor: Prof. Bhaskar Ramamurthy, I.I.T Madras); Completed in Dec-1992. This realizes an optimum receiver. The equalizer was simulated in C-language and implemented on an ADSP-2101 chip.

3. Title Study of Desired Radiation pattern from a line source for tracking radar application. Details For B.E (Advisor: Prof. G. S. N. Raju, A. U. College of Eng.); Completed in June-1991. This C-language simulation studies the trade-offs of the radiation pattern by controlling the aperture function of the antenna.

12 Student Projects mentored

S1: Title: An Efficient Realization Of Discrete Multitone Modulation in DSL Modems Year: At Texas Instruments in 2002

Student: Ms. Preethi Premkumar, Bachelor in Electrical Engg., Birla Institute Of Technology and Science, Pilani.

S2: Title: Transforming Linear Prediction Coefficients to Line Spectral Pairs and Line Spectral Frequencies for Speech Codecs.

Year: At Motorola India Electronics (Pvt.) Ltd., in 2001 Student: Mr. Naresh Rekhapalli, Masters in Electrical Engg., in Digital Systems and Communication Engi- neering, National Institute of Engg., Calicut, Kerala. 6-8

S3: Title: Design of a two channel nearly perfect reconstruction filter bank and efficient implementation of a general Cosine Modulated Analysis Filter bank on Motorola DSP566xx.. Year: At Motorola India Electronics (Pvt.) Ltd., in 2000 Student: Mr. Charan. M.N, Masters in Electrical Engg., in Digital Electronics and Advanced Communica- tions., National Institute of Engg., Suratkal, Karnataka. S4: Title: The PM1 algorithm implementation on Motorola’s DSP566xx. Year: At Motorola India Electronics (Pvt.) Ltd., in 1999 Student: Mr. Harsha Deep Gadi, Bachelor in Electrical Engg., Birla Institute Of Technology and Science, Pilani.

13 Recognition

1. Award by Texas Instruments(TI) for the SELT patent [PT2] disclosure. 2. Best paper citation for the paper [C4].

3. Award by Motorola India(MIEL) for 3G-FEC (Forward Error Correction Code) project in recognition and appreciation of outstanding performance and valuable contribution in 1999. 4. An efficient algorithm which locates the roots of a second order error locator polynomial in Galois Field. This also bagged the encouragement award by MIEL, for technically innovative contribution in 2001 after successful field trials.

5. Award by MIEL for Voice Pager Project, for contributing to the best practice quantitative control of in process faults in 1998.

14 Academic Merits

1. Graduate Aptitude Test in Engineering (GATE), Percentile 97.25 in 1991. 2. Andhra University First Rank in B.E in 1991.

3. Andhra University Eighth rank in Matriculation (10th Standard) in 1985. 4. Recipient of National Merit Scholarship during 1985 - 1991 based on the distinction in Matriculation from Andhra University.

5. Recipient of Telugu Vigyana Parithosakam during 1987 - 1991 based on the distinction in PUC(/12th) from Board of Intermediate Education Hyderabad.

15 Workshops Attended

1. A six day workshop on Business Analytics by Indian Statistical Institute, Bangalore in Nov-2016. 2. Presentation Skills, Conflict Management, Interviewing Skills, Personal Effectiveness, Team Building, Per- sonality Development(Landmark Forum).

3. A three day workshop on Wavelets and Filter Banks at I.I.T Mumbai, in Dec-1998. 7-8

16 Education

Qualification Institution Year Score

PhD in Signal Processing

{Spectral Estimation, Linear Algebra}

Indian Institute of Science,

Bangalore.

Jan-2010

6.5 CGPA

(8-point)

M.Tech(Master of Technology) in Com-

munication Systems & High Frequency

Technology.

Indian Institute of Technology,

Madras.

Jan 1993

7.73 CGPA

(10-point)

B.E(Bachelor of Engineering) in Elec-

tronics & Communications

College of Engineering,

Andhra University,

Visakhapatnam

July 1991 82.76%

Intermediate(12th/Pre-University)

Maths,Physics, Chemistry

Board of Intermediate Education,

M/s A. V. N. College,

Visakhapatnam

July 1987 81.3%

Matriculation (10th) Maths, Physics

Andhra University,

Visakhapatnam

March 1985 83.6%

Rastra Basha(National Language - Hindi)

Dakshin Bharat Hindi

Prachar Sabha, Madras

August 1983 60%

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