Committee Member Technology Manager

Saurabh Desai

Fremont, CA ***** 408-***-****

admqf1@r.postjobfree.com linkedin.com/in/saurabh-desai-b636707

Technology Manager

Define, Develop & Lead High-Profile Technology Initiatives & Supply Change Management

Drive Foundry, Process & Quality for Manufacturability

Insightful, forward-thinking leader with extensive experience in process and package engineering and foundry technology management. Quality-minded problem solver with solid understanding of semiconductor process integration and reliability. Highly skilled in influencing and empowering staff to achieve results within deadline-driven environments.

Core Strengths:

Foundry Management Process & Package Technology Development Operations Supply Chain

Yield Improvement Program & Project Management Budgeting Team Leadership

Key Accomplishments

Managed process and package engineering teams (30+ engineers) and budget of >$7M.

Developed integrated CMOS, Power BCD, RF and SOI technologies. Development included technology roadmap, TCAD, TEG, fabrication, modeling, reliability, electrical design rules (EDR) and release to production.

Provided foundry management for BCD, mixed-signal analog, RF, MEMS, GaN and CMOS technologies. Worked with foundries on technology evaluation, selection and manufacturability.

Oversaw technical aspects of foundry / subcontractor supply chain management. Worked with Asian fabs (TSMC, GF, Vanguard) and assembly (ASE, Amkor, Carsem) for technology selection and yield / defect improvement.

Managed quality and worked with suppliers and internal groups, ensuring performance met reliability metrics. Conducted audits of subcontractor facilities and created quality / reliability matrix (QRB, PCN).

Implemented defect reduction and yield improvement programs in fab and at product level.

Collaborated with various groups (design, foundries, supply chain, purchasing and finance), driving successful process and package technology roadmaps and implementation.

Reviewed external BCD, mixed-signal and RF / SOI foundry technologies. Benchmarked FOM against product requirement and drove technology roadmap.

Directed cross-functional teams, including process, package, design, supply chain, purchasing, quality and manufacturing.

Drove and implemented process improvements and implemented quality improvement programs (DOE, Six Sigma, FMEA, DFM, 8D, QRB and cost reduction).

Worked with manufacturing sites in Taiwan, Japan, Malaysia, South Korea and Germany.

Developed and implemented methodology of technology development from feasibility and development to deployment and manufacturing release.

Initiated GaN research programs with IMEC (Belgium) and developed technology.

Earned 13 patents in field of semiconductor devices.

Saurabh Desai admqf1@r.postjobfree.com Page Two

Professional Experience

RENESAS CORPORATION (formerly Intersil), Milpitas, CA 2012 - 2021

Senior Manager, Technology

Led development of next-generation power and radiation-hardened technologies. Planned and coordinated all engineering builds at supplier locations to ensure timely release to production. Worked with business units (BUs) and design team to develop technology roadmap (process and package engineering). Managed modeling, ESD, reliability, integration, package development and project management groups.

Defined and created competitive LDMOS power process at Japan fab, achieving best-in-class figure of merit (FOM).

Drove power process development at foundries in Asia (TSMC, Vanguard), providing design with differentiated technology with competitive Rdson.

Provided foundry management of BCD, MEMS, RF, CMOS and GaN technologies. Interacted extensively with foundries for process selection, business, manufacturability, quality and audit, ensuring best-in-class technology for next-generation product roadmap.

Directed product yield improvement through device architecture, fab defect reduction and fab equipment, resulting in >95% cumulative yield for fab, test and assembly for automotive flow.

Acted as foundry interface for TSMC, Samsung and Vanguard Zero for next-generation process, yield and quality improvement.

Collaborated with internal and external groups, meeting process and package quality, reliability and manufacturing goals.

Worked with packaging subcontractors for WLCSP, QFN and modules package selection for differentiating technologies.

TEXAS INSTRUMENTS / NATIONAL SEMICONDUCTOR, Santa Clara, CA 2000 - 2012

Manager, Technology

Managed Texas Instrument’s high-speed BICMOS roadmap and technologies. Collaborated with business unit and marketing to define silicon technology roadmap. Led integration, process, reliability and program management groups. Developed high-speed SiGe (>200 GHz) and low Rdson power technologies.

Served as yield champion for products and process through device architecture and defect reduction.

Oversaw SiGe research program on 0.18um CMOS node with IMEC (Belgium) and transferred developed process to manufacturing in USA fab, enabling high-speed next-generation products.

Built integrated trench and low-cost discrete FET at UK fab and power processes at Dallas, TX fab.

Education

Master of Science in Electrical Engineering (MSEE), Santa Clara University, Santa Clara, CA

Master of Business Administration (MBA), Operations Management, National University, San Jose, CA

Bachelor of Science in Electrical Engineering (BSEE), University of California, Berkeley, Berkeley, CA

Professional Affiliations & Community Involvement

BCTM Executive Committee Member & Local Chair, BCTM Conference

LV Power Device Committee Member, International Symposium on Power Semiconductor Devices (ISPSD)

Volunteer photographer for non-profit organizations

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