KARUMANCHI SURYA

Email: admmw3@r.postjobfree.com

Skype Id: karumanchi.909_1

Contact: +91-812*******

Career Objective:

To best utilize my technical and life skills to secure a professional career in a competitive global environment with ample opportunity to tackle the challenges and advance, while continuously building on my knowledge and skills. Educational Qualifications:

M. Tech VLSI Design (2017-2019 & 73.2 %) from VIT University, Vellore.

B. Tech Electronics and Communication Engineering(2012-2016 & 71 %) from Bapatla Engineering College, Bapatla.

Intermediate (2010-2012 & 92.4 %) (MPC) from Sri Chaitanya Educational Institutions, Vijayawada.

SSC (2009-2010 & 92 %) from Viswabharathi E.M High School, Gudivada. Tools and Languages:

Design: Cadence Virtuoso, Xlinx ( Vivado & ISE Design Suite ), Model Sim. Languages: Verilog, C, Python.

Scripting Languages: TCL.

CAD Tools: Synopsys IC Compiler (28nm, 45nm and 90nm). Areas of Interest:

Digital Logic Design, Verilog Programming, IC Design, STA. Online Certifications:

Certificate of completion for Complete Python Bootcamp from Udemy.

Online Certification course on Data Science and Machine learning using Python with B Grade from NIELIT, Chennai.

TCS NQT Score Card with 75% ( 1352/1800 ) normalised score. Professional Experience:

Physical Design Trainee in Sion Semiconductors Pvt Ltd., Bengaluru from July 2019 to January 2020.

Role:

Involved in performing sanity checks, design export, preparing floor plan, power plan, placement, trial route and detailed routing.

Projects:

Block 1:

Tools: Synopsys IC Compiler

Aspect Ratio: 1.8906

Core Utilization: 87.2%

Gate Count/Area: 2, 95,935/ 1062025.81 um^2

Macros /STD Cells: 12/27096

No. of Clocks: 17

Frequency: 200MHz

Technology: 28nm

Block 2:

Tools: Synopsys IC Compiler

Aspect Ratio: 0.9986

Core Utilization: 85.4%

Gate Count/Area: 2, 96,296/ 1508801.9 um^2

No. of Clocks: 17

Frequency: 225 MHz

Technology: 45nm

Academic Projects:

Master Thesis:

Design of Low power High Immune SEU tolerant TMR Latch. Description: For digital system designs, TMR latch is the most commonly used latch in aerospace applications such as in military or space systems. The TMR latch includes three simple identical latches and a majority voter circuit. The Fault tolerance MV circuit plays a key role in ensuring the correct logic of the TMR scheme. The main theme of the project is decreasing number of MOS transistors, number of sensitive nodes for decreasing power compared to previous hardened TMR latches.

Other Projects:

1. Design of 5 bit flash ADC for thermometer code to binary code conversion using transmission gates.

Description: The designing of a thermometer code to binary code is one of the bottlenecks in achieving high speed. The process involved is that an encoder circuit translates the thermometer code into the gray code to reduce the effect of meta-stability and reduction of bubble errors. The main theme of the project conversion of 32 bit thermometer code to gray code and then to binary code using xor gate and adders with transmission gates.

2. Design of a three terminal memristor and study of V-I characteristics on basis of two terminal memristor.

Description: We know that resistor, capacitor and inductor are basic electronic components. But in 1971, we came to know about two terminal memristor in which present resistance depends on amount of electric charge flowed in the past. So, the main theme of the project is to otain V-I characteristics of gated memristor in cadence virtuoso by use of Verilog-A code.

Declaration:

I hereby declare that the above written particulars are true to the best of my knowledge.

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