Professional Training:

Certified Physical Design training from ChipEdge Technologies Pvt Ltd, Bengaluru using Synopsys IC Compiler-I, IC Compiler-II.

Tools used in the Training:

Synopsys EDA Tool:

IC Compiler-II

Star-RC – RC Extraction

IC Validator – Physical Verification

PrimeTime – Timing Closure

Course Outline:

Familiar with ASIC Design flow.

Worked on EDA Synopsys tool and having good exposure to IC Compiler I,II (ICCI,ICC2) tool.

Debugging the issues and improving timing, Congestion and DRC solving.

Basic knowledge on Static Timing Analysis (STA).

Knowledge with Physical Verification and ECO flow. Education:

Year Degree/Examination University/College/Board CGPA/Percentage 2021 M.Tech (VLSI Design & Embedded Systems) JNTUA/GVIC/AP 76 2017 B.E (Electronics & Communication) JNTUA/SSITS 73 2013 12th Standard S.B.T.R.M/AP 82

2011 10th Standard ZPH SCHOOL/AP 75

Projects:

Efficient Vlsi Architecture Of Fault Tolerant Tcam Using Magnitude Comparator: The objective of the project is to design a lossless data compression system which operates in high- speed to achieve high compression rate, by using architecture of compressor, the data compression rates are significantly improved. Also inherent scalability of architecture is possible. Tools: Xilinx ISE 14.5

Pattern-Recognition using Digital Image Processing Techniques: This paper describes object, face and text detections based on the pattern recognition techniques. The goal of this project is to describe the recorded video face detection by manipulating the machine and image processing.

Tools: MATLAB-2016.

VEERANJANEYULU D

Contact No: +91-891*******

Email-ID: admk4c@r.postjobfree.com

An innovative mind-set with a vision to achieve development at Personal and Organisational level Technical Skills:

Tools:

Synopsys: IC Compiler-I, II

Cadence: Encounter

Xilinx: ISE

Programming Language: Verilog, Tcl, Python.

Project on Physical Design flow:

Block 1:

Technology: 28nm/ 9 Metal Layers

Gate Count: 300k+

Macros: 16

Standard Cells: 71549

Number of Clocks: 4

Frequency: 350MHz

Area of Interest:

Digital Circuit Design

ASIC Design

STA

SoC

Low power design

Block 2:

Technology: 28nm/ 9 Metal Layers

Gate Count: 50k+

Macros: 6

Standard Cells: 10K

Number of Clocks: 3

Frequency: 500MHz

Role:

Design Import, Sanity Checks, Floor planning, Power planning, Placement, CTS, Routing, Timing Analysis & Optimization, Physical verification and ECO flow.

PnR is done for the Block 1 & 2 with the above-mentioned steps.

Debugging the issues and improving Timing, Congestion and DRC solving. Workshops on VLSI in Cadence Tool:

Attended three days workshop on “PHYSICAL DESIGN” conducted by ULSI Academy Bengaluru, in GVIC angallu held on July 26st,27 and 28 /2019.

And also done 33 Hours of VLSI- PHYSICAL DESIGN course in udemy on 07 NOV 2019. Strengths: Leadership skills, Team player, Practical approach, Quick learner. Declaration: The above furnished details are true to the best of my knowledge.

(Veeranjaneyulu D)

Contact this candidate