YAMINI SABBINEN admjzf@r.postjobfree.com

814-***-****

SUMMARY:

B. Tech in Electronics and Communication with 86% from Acharya Nagarjuna University

Completed 6 months of Custom Layout Training at Sumedha Institute of Technology from September 2018to May 2019

Having in depth knowledge of Custom Layout Design and Verification

Working experience on projects in CADENCE VIRTUOSO Schematic and Layout design and Project in both analog and digital layout design platform with minimum area utilisation

Layout designed by estimating area, Floor planning, Routing and power mesh good at resolving DRC, LVS using calibre as well as assura

SKILLS & TOOLS:

EDA Tools: Cadence VXL, Virtuoso Layout/schematic Editor

Verification tools : Assura,Calibre,PVS (DRC,LVS, ERC, Antenna Effet,EM,Latch-up)

Platform: Linux/Windows Environment

Technology: GPDK-45nm,TSMC-16nm(FINFET),TSMC-28nm(worked on 6TSRAM)

PROJECTS EXECUTED:

Project 1: DACand it's sub blockd

Block : Layout design of current mirror

Technology: TSMC-16nm

Roles. : Layout design and verification

Responsibility: 1. For the given schematic area estimation and floor planning is done for the given input and outputs .placement of device has been done based on current flow with fixed height.

2.Critical routing was done i,e without crossing any active devices and then verified LVS and DRC for the current mirror.

3.Usage of guard rings to avoid Latch up problem and dummies used for resistor to avoid noise .

Block. : Layout Design of Op-Amp Technology: TSMC-16nm Roles : Layout Design and Verification

Responsibility:1. Interdigitation Matching used for Current mirror and Common centroid matching used for Differential Amplifiers to reduce process variations .

2.Symmetric routing was done to achieve common centroid matching for differenal pair to get equal delay .

3. Verified DRC and LVS for the Op-Amp layout.

Block. : Layout Design of Inverter and Pass transistor switch

Technology: TSMC-16nm

Role : Layout Design and Verification

Responsibility : 1. Placement of device has been done based on current flow and verified input and output signal flow and power mesh was done for equal distribution of power.

2. Metal width taken accordingly to meet the current flow and avoid EM and higher metals used for routing at top level to avoid Antenna effect .

3.Layout is made as compact as possible and in square shape and tried to maintain more than one via .Tried to reduce parasitics while routing

Project 2: Standard cells

Block: Layout Design of Full Adders & Decoder

Technology: GPDK-45nm

Roles : Layout Design and verification

Responsibility: 1. Design the layout and schematic of Full Adder and Decoder using virtuoso tool and worked on full adder of different types and estimated the area and complexity of each design.

2.Verified DRC and LVS for the design using Assura tool.

Block : Layout Design of standard cells Technology : GPDK-45nm

Roles. : Layout Design and Verification

Responsibility: 1. The main objective of the project is to design the layout and schematic of standard cells using virtuoso tool and worked on full adder of different types

2. estimated the area and complexity of each design and Verified DRC and LVS for the design using Assura tool.

3. Routing done using Metal 1only.

EDUCATIONAL QUALIFICATION:

Qualification

Stream

Board/University/

College

Year of

passing

Percentage

B. Tech

ECE

Bapatla Women’s

Engineering

2018

86%

Diploma

ECE

State Board of Technical Education

2015

79%

SSC

Rama Krishna Public School

2012

83%

CO -CURRICULAR ACTIVITIES:

Actively participated in cultural Activities Participated in work-study in college&Got participation certificate in Fire and safety conducted by the Kings Institute of Fire & Safety Engineering.

Attended work shop on Robotics.

Attended internship in Effectronics System Pvt. Ltd in Quality Management and Testing.

Participated in It Olympiad and Participated in Youth Empowerment Program in Lions Club OF Guntur main.

Actively participated in Ncc activities .

DECELERATION:

I am here by declare that all information above is true to the best of my knowledge.

Place:

Date: S.YAMINI

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