Ashok Manager

CURRICULUM VITAE

MOHIT

#***, ***** ***, ****** ** .6, New

Ashok Nagar, New Delhi, 110096.

Email-id: **************@*****.***

Mobile no: 797-***-****

CAREER OBJECTIVE:-

To work in the environment where I can utilize my knowledge and technical skills, contributing to growth of the organization.

EDUCATIONAL QUALIFICATIONS:-

Degree University/ Board Year Percentage/CGPA

M.Tech(VLSI

DESIGN)

J.C.Bose.

UST,YMCA,Faridabad

2019-2021 7.27

B.Tech (E.C.E.) Dr .A.P.J. AKTU, U.P. 2012-16 74.54 12th P.S.E.B 2012 83.3

10th P.S.E.B 2010 69.68

TECHNICAL SKILLS:-

HDL : Verilog.

HVL : System Verilog.

Methodology : UVM.

Programming Language : C.

Scripting Language : Linux (bash shell).

Tools : Xilinx ISE, Questa sim.

Interface Protocol : I2C, SPI, UART.

Bus Protocol : AMBA APB, AHB.

Minor Project:

1) RESET – MANAGER UVM ENVIORNMENT

Description:

• Designing and verification done from documents provided by institute. In verification, I use UVM environment to verify this design.

• This environment consist of multiple classes like sequence, sequencer, driver, monitor, and agent etc.

• This is reset manager module, which control the functionality of other reset of sub module and I verify that using UVM.

2) CLOCK - MANAGER UVM ENVIORNMENT

Description:-

• In this project verification is done by UVM and project is about clock division in sub modules. In verification, I use UVM environment to verify this design.

• This environment consist of multiple classes like sequence, sequencer, driver, monitor, and agent etc.

• Basically there are two output clock, which are provided to digital and analog sub module.

PERSONAL DETAILS:-

Mother’s Name : Mrs. Kamlesh Rani

Father’s Name : Mr. Shiv Shankar

Date of Birth : 03/07/1995

DECLARATION:-

I hereby declare that the above mentioned information is correct up to my knowledge and I will solely be responsible for any discrepancy found in them. Place: New Delhi MOHIT

Date:-

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