Project Telugu

Name: Babu Renangi

Email: *************@*****.***

Contact No:709-***-****.

Objective:

Pursue a challenging career in the field of DFT leading to professional as well as personal growth and to contribute to the organization by utilizing my skills, knowledge and abilities.

Academic Profile:

● Bachelor of Technology, Electrical & Electronics Engineering from Jawaharlal Nehru Technological University Anantapuram in the Year April/May 2019 with an aggregate of 76.5%.

● Intermediate, State Board of Intermediate, Andhra Pradesh in the Year March/Apr 2015, with an aggregate of 70.8%.

● Secondary School Certificate from Board of Secondary Education, A.P in the Year March/Apr 2013, with an aggregate of 77%. Professional Summary:

● Good knowledge on Digital Electronics and VLSI ASIC flow.

● DFT compiler on Scan Insertion at block level.

● DFT compiler on Compression at block level.

● Scan implementation plan at block level.

● Pattern generation using Tetramax.

● Stuck-at & Transition faults on block level ATPG.

● Good understanding of JTAG, Wrapper Cells.

Professional Training:

Completed Design for Testability (DFT) training from ChipEdge Technologies Pvt.Ltd, Bangalore, using Synopsys tools during June to Sep 2019. Course Outline:

ASIC Flow, DFT fundamentals, SCAN Design, SCAN DRC, SCAN Insertion, Scan Compression, Boundary Scan/JTAG, Fault models, ATPG Coverage, ATPG for Stuck-at and Transition fault models, Pattern simulations, Debug simulation failures. Tools used:

DFT Compiler, Tetramax, VCS and BSD Compiler.

Projects:

Project 1: Scan insertion and DRC analysis.

Technology : 28nm

Design : Design with 16k flops

No. of Clocks : 2

Tools Used : DFT Compiler

Role :

Performed Scan insertion by defining constraints and different scan configurations. Analyzed and fixed Scan DRC violations. scan insertion with Compression logic.

Project 2: ATPG pattern generation and simulation for Stuck-at and Transition fault models.

Technology : 28nm

Design : Design with 11k flops

No. of Clocks : 2

Tools Used : Tetramax for ATPG and VCS for simulations Role :

ATPG pattern generation for Stuck-at and Transition fault models. Generated Basic and fast sequential patterns using Tetramax. ZERO delay and SDF based Chain and Scan pattern simulations. Software proficiency:

● Verilog HDL.

● MS-office.

● LINUX operating system.

Personal Strengths:

● Able to work independently and as a part of team, with a high degree of integration.

● Resourceful and a good solution provider with an excellent communication and presentation skills.

● A quick learner with an inquisitive mind, committed to pursuing personal development.

● Expertise in “Time Management “and efforts to ensure optimum effectiveness. Academic project:

Project name : Design Combinational Circuits using reversible decoder Client : B. Tech project

Period : 04 months

Team size : 04 members

Project description :

● The aim of this project is to realize different types of combinational circuits like full-adder, full-subtractor, multiplexer and comparator using reversible decoder. Personal Details:

Name : Babu Renangi

Date of Birth :16 - 03 -1998

Sex : Male

Nationality : Indian

Marital Status : Single

Languages : Telugu, English.

Personal Details:

I do hereby declare that above stated particulars are true, complete and correct to the best of my knowledge and belief.

Date:

Place: Bangalore. (Babu Renangi)

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