JELLA HEMASUNDAR REDDY

Galiveedu,Kadapa, Andhra Pradesh. Pin : 516267

995-***-**** admek6@r.postjobfree.com

OBJECTIVE

An enthusiastic and self-motivated electronics engineer looking for a challenging and responsible position as Physical Design engineer to apply my knowledge and skills with my hard work and patience. EDUCATION

Vlsiguru

2020

Physical design

A

Jntua University

2020

Electronics and communication engineering

73

St.Joseph's jr college

2016

MPC

74

Board of secondary education

2014

10 th class

87

SKILLS

Domain working in complete PD flow from RTL to GDSII Place and routing : Icc2_shell Platform :linux Good Knowledge on VLSI design and CMOS technology CHIP and Block level Floor planning, analysis of floorplan options taking into account timing and area budgets PROJECTS

28nm design, 450 MHz

Overview: 28nm,450 MHZ

Shape: rectilinear

Environment: ICC2_ Shell

BLOCK LEVEL FLOOR PLANNING AND POWER PLANNING

Description:

Placing Macrpos (hard macros) in core area.

Thereby determining the routing areas between them and creating power grid network to distribute power to each part of the design equally.

Challenges:

Port comunication, Macro to Macro communication.

Macro grouping (logical hierarchy).

Spacing between Macros.

BLOCK LEVEL PLACEMENT & ROUTING AND CLOCK TREE SYNTHESIS Description:

Performing Timing driven and legalised placement of standard cells by ensuring Congestion free and good routability.

Clock Tree Synthesis is to connect clock ports with clock pins and building a Clock Tree to meet timing requirements.

Challenges:

To control congestion and for timing convergence tried different floorplan experiments and implemented different strategies.

Making Clock skew within the target by adding buffers/inverters to clock path. Tried different clock tree synthesis flow.

STATIC TIMING ANALYSIS FOR TIMING PATHS

Description:

Analysing Setup and Hold Slack timing reports which are dealing with Derate, Uncertainity, CRPR,Multicycle and Multi frequency paths by reporting the violations in the logical DRC's. Challenges:

Identifying and constraining various timing paths and calculating setup and hold slack. Analysing the various timing reports which are generated due to PVT corners, OCV, and analysing path with CRPR. Understanding the concepts and usage of timing exceptions such as false path and multicycle path. Setting up multicycle timing exception on particular pins to meet the timing.