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Email address: admc16@r.postjobfree.com

Nationality: Indian

Gender: Male

Date of birth: 26/04/1998

WORK EXPERIENCE

Analog Layout trainee

Vlsi Guru Training Institute [ 01/12/2020 – Current ] City: Bangalore

Country: India

Industrial training on VLSI Design using Industry standard tools and implementation concepts in 28 nm technology. In depth knowledge on Layout Design and DRC,LVS concepts. Worked on a few implementation projects in 28 nm technology from floorplan,placement, routing followed by DRC and LVS using Industry standard tools like Synopsys Custom Compiler.

Mentor

Karkhana Makerspace [ 01/10/2020– 1/03/2021 ]

Country: India

Mentoring and sharing the knowledge of electronics and circuit designing to the school and college children in partnership with Microsoft training program.

Student Intern

Lucents Technologies India Pvt.Ltd. [ 01/01/2020– 01/04/2020] City: New Delhi

Country: India

Learn several concepts of electronics and electrical closely worked with engineer from Noida Power Company Limited and megger group. My role here is to examine the Electrical resistance measurement device by comparing the data given by engineer with ideal data and providing assistance in case of any device failure. Summer intern

National Institute of electronics and information technology (NIELIT) City: Lucknow

Country: India

EDUCATION

Bachelor of Technology (B.TECH)

Ambalika institute of management and technology lucknow [ 2016 – 2020 ] Field of study: Electronics and communication Engineering Final grade : 1st Division With Honours with an aggregate of 78 % Suraj Pal Singh

Mobile No: +(91-945*******

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Synopsys Custom Compiler 28nm

Scripting

TCL

Programming

C / Verilog/SV

Operating system

Windows / Linux

Layout skill

Latch-up /Antenna Effect / LOD effect / ESD / Matching /Shielding / area and routing efficient layout PROJECTS

Digital Layout : Designing of standard Cells

Technology Node : Synopsys 28nm

Cells : INVERTER, NAND,NOR,EXOR,AND

Role : Developed a layout from a schematic and cleaned DRC,LVS Analog Layout : Designing of analog block

Project 1 Level Shifter

Technology Node: 28nm

Role : Developed a layout from a schematic and cleaned DRC,LVS Project 2 Operational Amplifier

Technology Node : 28nm

Role : Developed a layout from a schematic and cleaned DRC,LVS Challenges : Meeting the matching techniques for critical devices like differential pair and current mirror. Maintain metal width according to current rating and all critical nets should have some parasitic.

Project 3 Phase Locked Loop

Technology Node : 28nm

Role : Developed layout of VCO,charge pump, phase detector from a schematic and cleaned DRC,LVS

Challenges : Sharing of devices, area minimization and routing issues, matching must be there in layout by proper techniques.

Project 4 Digital-to-Analog Converter

Technology Node : 28nm

Role : Adjusted M1 and M2 Pattern error by adding filler cell and metal fills Cleaned DRC, LVS using the CPDS.

Challenges : Symmetric Routing and area minimization by sharing concept Analog SKILLS

EDA Tools

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Technical Skills

Development of layout with given constraints.

Proficient in DRC,LVS debugging.

Understanding the signal flow to acquire an optimum floor plan

Strong digital fundamental

Semiconductor Device physics

Cmos

Declaration

I declare that all the information given above are true and correct to the best of my knowledge and belief .

Place :Bangalore Suraj Pal Singh

Date :

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