BRYAN ANH LAI

**** ****** *****, *** *****, CA **126

858-***-**** (cell)

adluej@r.postjobfree.com

Objective

Obtain a full time position as a Digital Verification Engineer or Digital Design Engineer.

Experience Highlights

Experience with Universal Verification Methodology (UVM) using SystemVerilog language.

Experience with QuestaSim Verification IP (QVIP) for AXI-Lite, AXI4, AXI-Stream, Ethernet, Avalon-Memory-Management, and Avalon-Stream interfaces.

Working knowledge of UVM Template Generator and QVIP Configurator to create UVM test-bench.

Experience with Open Source VHDL Verification Methodology (OSVVM) using VHDL language.

Working knowledge of QuestaSim/ModelSim commands, do file, Makefile, Bash/Shell script in Linux environment.

Working knowledge of verification planning, test plan based on specification.

Experience with RTL design for Xilinx FPGA, Xilinx and Altera CPLD using VHDL language.

Working knowledge of bus interfaces: AXI, PCIe, Ethernet, SPI, UART, USB, I2C

Experience with Xilinx IP and discrete components: FIFO, BRAM, Flash memory, DAC, ADC, Voltage regulator.

Working knowledge of software Xilinx Vivado/ISE and Intel Quartus.

Lab debugging using Xilinx Integrated Logic Analyzer (ILA), Chipscope, Logic Analyzer.

Skill of schematic drawing for Digital circuits using Mentor Graphic PADS.

Basic knowledge of Microsoft Office: Words, Excel, Visio for work documentation.

Holding DOD secret level security clearance

Employment History

Principal Design Digital – Northrop Grumman, Mission System, San Diego, CA (08/2016 – present)

Responsible for design of a UVM test-bench and test cases to verify functionalities of VHDL HDL Transceiver design in Intel Stratix 10 SoC. The QVIP modules for AXI-Lite, AXI-4, and AXI-Stream interfaces are deployed in the UVM test-bench. Test Sequences are implemented for test cases with functional coverage.

Responsible for design of a UVM test-bench and test cases to verify the transaction of UDP IPv4 data packets for the Low Latency Intel MAC PHY 100G Ethernet IP. The QVIP modules for Ethernet Serial TX/RX and Avalon interfaces are deployed in the UVM test-bench. Test Sequences are implemented for test cases with self-checking scoreboard.

Modifying the OSVVM test-bench and writing VHDL codes to implement the test cases of verification for AMCTR design in the Xilinx Zinq SoC.

Responsible for design of the Trusted Gateway Interface-CAIC FPGA (TGIF-C FPGA) module using VHDL language. FPGA is Xilinx Kintex UltraScale FPGA. The TGIF-C FPGA is a gateway which providing message transfer between the Power PC Host Memory and two Texas Instruments XIO2213B ICs (PCI Express to 1394b OHCI with 3-PORT PHY).

Digital Engineer II - Cobham Advanced Electronic Solutions, San Diego, CA (04/ 2007 – 08/2016)

Responsible for VHDL firmware designing and sustaining of FPGA/CPLD based Digital Integrated Module Assembly (IMA):

Designing/Drawing the FPGA/CPLD schematic based on block diagram/specification.

Coding VHDL for FPGA/CPLD firmware to perform the expected functionalities defined in the customer specification and firmware design document.

Analyzing the timing report and fixing any timing failure

Simulating the HDL design files using Mentor ModelSim.

Designing Test Interface boards and their harnesses which interface between Device under Test (DUT) and Universal Test Board (UTB).

Developing a VHDL test firmware for the UTB to send stimulus to DUT and read back the status data.

Collaborate with the RF engineers to integrate the digital subassembly into the Top Assembly Unit.

After transferring to production, sustaining the digital test, troubleshooting RMA, and supporting customer to resolve digital issues or update new features

Education

Bachelor of Science in Computer Engineering (Dec 2006)

San Diego State University, San Diego, CA

Certificate of Integrated Circuit Design (Nov 2014)

UCSD Extension, San Diego, CA

Association of Science in Electronic Technology (May 2000)

San Diego Community College, San Diego, CA

References

Available on request

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