Dr. James V. Nguyen

US citizen

**** ******** **, *** *** Melbourne, FL 32934

Phone: 321-***-****

Email: adldrh@r.postjobfree.com

EDUCATION

Bachelor in Science in Electrical/Electronic Engineering California State University Long Beach, California, USA 1996

Master in Science in Electrical Engineering

California State University Long Beach, California, USA 2001

Ph.D. in Industrial Applied Mathematics in Engineering Claremont Graduate University, Claremont, California, USA 2009

Current security clearance: Secret 8/2019

EXPERIENCE

BENTLEY GLOBAL RESOURCE (Contractor) 2019 – present

(Worked at Lockheed Martin site)

Senior Electrical Engineer II

● FPGA design for Missiles and Fire Control department. Working with the FPGA design team on the payload controller system. The firmware design includes the embedded microprocessor, Cortex ARM A9 that is used to handle all the flow data among components in the whole design. There are many IP cores used in the firmware design, such as, AXI4-LITE, IIC, GTX, UART, XADC, GPIO, MAC, CAN, DMA, QSPI, PSI, Ethernet, USB, SerDes, and DDR. These interfaces guarantee the proper communication among internal FPGA components as well as external devices, such as, DDR3, flash boot, sensors, fiber optic transceiver, and PC work station.

● DSP FPGA design for satellite and radio communication products: design Digital down-converter (DDC), Digital up-converter (DUC), CIC-Decimation, CIC-Interpolation, FIR-Decimation and FIR-Interpolation filters. Phase array antenna, phase delay and alignment circuit designs. Task: hardware and software review, design, and inspection. Tools: Vivado, ISE, HLS, Simplicity, and Modelsim, Quartus Altera/Intel FPGA Languages: C, VHDL, Verilog, SystemVerilog, and Matlab. Devices: Zynq 7030 and Zynq Ultra Scale + System on chips. Devices: Arria System on chips (Altera/Intel).

Documentation management tool: IBM Rational Synergy

RAYTHEON MISSILE SYSTEMS 2016 – 2019

Senior Electrical Engineer II

Firmware FPGA designer for Digital Configurable Logic Testing Center. Task 1: FPGA design to test the functionalities of the production boards. I am working with my firmware team. We develop the firmware to test the UUTs. Most of the time I modify the old firmware to produce the new one that meets the new testing requirements or specifications. The FPGA design is used to conduct all types of testing on UUT. It is like a processor. The PC users are able to make a request to UUT for functional verification through FPGA which is mounted on the fanout board. Task 2: Participate to the Product Quality Control group: using the Test Error Analysis Report (TEAR), TEAR Handbook as the guide to analyze the analog and digital circuit designs of the CCA to obtain all the tolerances from the cable and wiring resistances and all electronics components. The test equipment uncertainties are also taken into account in determining the product quality. Task 3: Technical writing: Write up the test procedure for Unit Under Test (UUT), the architecture of the FPGA design, and the report for the TEAR.

Task 4: Joint in to the mechanical design team: Create the Indenture Drawing List (IDL) of the whole system. MATHECORES 2010 – 2015

Senior DSP FPGA Engineer

• FPGA and Asic designs. Design PI cores for FPGA and ASIC on the mathematical function library, Image Processing, Digital Signal Processing (DSP), arithmetic functions, Signal Processing, Communication systems, Computer Vision Systems. Having experience of making more than 600 IP cores in VHDL and Verilog.

Having the strong VHDL, Verilog, and C experience that applies to the area of FPGA and ASIC designs. FPGA design experience with using high density Altera and Xilinx FPGAs in production including in-depth knowledge of using Altera and Xilinx along with integrating tool, Modelsim in the FPGA design and verification processes. These tasks get involved with prototype boards of design of digital signal processing module which contains many IPs cores described above.

• Software development: Tool used Visio Basic.

• Task: IP-Core generator’s application development IBM 2001 – 2005

Microelectronics Design Engineer

• Design and verifying of the digital ASIC. Conducting the static timing analysis, simulation, and running the complete test bench for the customers’ chips which are fabricated by IBM.

• Contribute all the phases of the whole design, such as architecture definition, RTL coding, simulation, and verification management.

• Worked closely with customers to develop test plans and actively participate in the debug phase

• Supporting customers in synthesis, DFT, and physical design phases. Raytheon System Company 1996 – 2000

Electrical Engineer II

• Work on schematic capture (by using Mentor Graphic design tool) on the existing radar systems for aircrafts and fighters. • Design and modify the existing communication systems.

• FPGA designs for the communication products of Enhance Positioning Location Report System.

• Convert old technologies design (schematic-based design) into VHDL codes.

• Trouble shooting and verify the FPGA design on the prototype boards in the laboratory with the digital signal Generators and oscilloscopes and digital programmable logic analyzers. Certifications and Awards:

• ASIC PROCESSING AND SIGNOFF Worldwide ASIC Education, IBM (February 2000)

• Radio Communication Training Hughes Training, INC (July 1997)

• Six Sigma certification (Quality Control) Raytheon Missile Systems (July 2017)