Engineer Power

HARSHEETA MOHILE

SANDEEPANI CERTIFIED VLSI ENGINEER

BE (Electronics &Communiction)

Phone: 832*******, Email: ************@*****.***

Proficiency:

HDL/HVL Hardware Programming

languages Tools

Verilog, SystemVerilog ZedBoard C (Basic) QuestaSim, Vivado a. HDLC FRAMER (High Level Data Link Control):

High Level Data Link Control (HDLC) is a bit oriented code transparent synchronous data link layer protocol developed by the International Organization for Standardization(ISO). HDLC frames can be transmitted over synchronous or asynchronous serial communication links. Those links have no mechanism to mark the beginning or end of a frame, so the beginning and end of each frame has to be identified. This i s done by using a frame delimiter, or flag, which is a unique sequence of bits that is guaranteed not to be seen inside a frame. This sequence is '01111110', or, in hexadecimal notation, 0x7E. Each frame begins and ends with a frame delimiter. A frame deli miter at the end of a frame may also mark the start of the next frame. A sequence of 7 or more consecutive 1 bits within a Frame to be aborted. The Project was developed in VIVADO Tool and completed the synthesis and implementation with 44 LUT(Look Up Tables ) and 56 flip flops.

b. TIMING CLOSURE OF BAUGHWOOLEY MULTIPLIER :

Multiplication represents one of the major holdups in most digital signal processing system. With advances in technology, many researchers have tried and are trying to design multipliers which offer high speed, low power consumption and hence less area in one multiplier thus making them suitable for various high speed, low power and compact implementation. To achieve speed improvements, Baugh Wooley Multiplication technique used for signed multiplication. The array multiplier Baugh-Wooley is an efficient way for multiplying both signed and unsigned numbers. Baugh Wooley algorithm is used in High Performance Multiplier (HPM) tree, which inherits regular and repeating structure of the array multiplier. Baugh Wooley multiplier exhibits less delay, low power dissipation and the area occupied is also small compared to other array multipliers. The architecture of Baugh Wooley multiplier is based on carry save algorithm.The Project was developed in VIVADO Tool and completed the synthesis and implementation with 27 LUT(Look Up Tables) respectively.

BOOTH MULTIPLIER

The main objective was to get some overview of Tool and check if the proper hardware is infered or not. It also Included the Timing Analysis of Design and Observation of all Timing Reports.

ROUND ROBIN ARBITER

The purpose was to observe the inferance of the proper hardware by the VIVADO Tool and observed the simulation results and utilization reports for the same Course Institution University /

Board

Aggregate

Percentage Batch

BE (Electronics &

Communication)

C.K. Pithawala College

of Engineering &

Technology, Surat

Gujarat

Technological

University

7.99 CGPA 2019

12th Presidency School GSEB 66.53 2015

10th Presidency School GSEB 81 2013

Awards & Achievements

Completed the government certified course of C programming

Attended the Raspberry Pie workshop held at college Campus

Attended the zonal as well as national college level technical fest (techfest) arranged in various colleges of Gujarat

Completed the Summer Training Session (Internship) at ONGC (Hazira Surat) Strengths

Good communication skills

Numerical Ability and analytical skills

Able to cope up with different situations and challenges

Enthusiasm in knowing unknowns

I do hereby confirm that the information given above is true and to the best of my knowledge. Harsheeta N.Mohile

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