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Semiconductor Manager

Location:
Fremont, CA, 94536
Posted:
April 30, 2021

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Resume:

John G. Wang

**** **** *****, *******, ********** 94536

510-***-**** (cellular), 510-***-**** (fax)

Objective

Seek the position for Senior Foundry Manager - Product Yield Enhancement with process development responsibility for semiconductor company. Also interested in project management for newly developed and/

or advanced technologies for its new products introduction from development/planning to commercialization

Experience

2010 to Now Marketing Director/K-Designers, Technical Consultant for global semiconductor companies

2006 to 2010 Consultant for global semiconductor process, material, equipment and IC designs

Semiconductor advisor with start-up IC design/fab-less company to search for its foundry partner:

consultant with 0.25um RF mixed-signal design to search for a foundry process company in Asia.

Process applications and global product management for Semiconductor Materials Company with advanced Cu plating processes. CMP consumables - slurries, pads for Cu, W and Oxide processes

Product Management - Sales/ Marketing for semiconductor instrumentation-company to integrate new products with advanced applications in 300mm platforms for a IC foundry company in Asia.

Strategic Marketing/ Sales for advanced software company in AEC/ APC to integrate its products with advanced applications in 300mm platforms for a semiconductor IC foundry company in Asia.

2002 to 2005 Abrasive Technologies Inc. Lewis Center, Ohio

Process Applications and Sales Manager based in Hsin-Chu, Taiwan. R.O.C.

Process and product applications, product management, sales and marketing for semiconductors and hard disks materials company with advanced pad conditioner. Sales and Marketing, process applications - customer technical supports and/ or product management for new accounts in Asia.

1999 to 2002 Lam Research Corp. Fremont, California.

Sr. Product Marketing Manager for Linear CMP/ CLN products. Responsible for developing technology roadmaps - technical marketing for Teres CMP with global semiconductor customers. Sr. Technical Manager for supporting Oxide and Cu in Best-Known Methods with consumables and post CMP clean processes. Setup process technology demonstration for customers worldwide. CMP/ CLN technical liaison for Oxide in direct STI and Cu for damascene process technologies Metrology module integration for 0.13um Cu lowk process technology for IC foundry companies

1997 to 1999 TSMC - Vanguard International Semiconductor Corp, Technology Development Division, Hsin-Chu, Taiwan/R.O.C. Director for Advanced Modules and Process Integration Division, Managed advanced module and process integration for 0.17um DRAM & 0.18um SRAM device. Process technology for Photolithography/ Plasma Etch/ CVD/Thin film/CMP module integrations and metrology. Processes technology development for STI, ILD/ IMD/ PMD, SAC Poly CMP and W Thin Films & W CMP for 0.19um/ 0.17um DRAM, 0.18um SRAM and 0.15um logic devices Process/ device technology development and process transfers from R & D to manufacturing line.

1996 to 1997 IPEC-Westech, CMP Process Applications Global Sales and Marketing, Phoenix, Arizona CMP Project Manager, process applications for oxide, W and Cu process. Responsible for new CMP process demonstrations, process support for its worldwide customers.

Designed experiments to optimize CMP processes with metrology and consumables (pad/ slurry). Performed process support for IPEC-472, 676 and 776 in qualifying process/ technology transfer.

1991 to 1996 Eastman Kodak Company, Corporate Research Laboratory, Rochester, New York

Program Manager - Senior Research Scientist in materials/ process for LED, CCD imagers. Responsible for developing/transferring/optimizing photolithography/plasma etch/CVD processes (LPCVD/ MOCVD for SiO2 and ZnO, PECVD for Si3N4) from R&D to pilot line for materials/ processes of GaAsP/ GaAs, AlGaAs/ GaAs LED, laser diodes of III-V opto-electronics and CCD/ CMOS imager sensors. Program Management for selecting capital equipment including Photolithography, Plasma Etch/RIE/PVD/CVD/Packaging. Started-up wafer pilot line, developed processes, devices, materials, reliability/failure analysis from R&D to pilot line for manufacturing

1987 to 1991 TRW Inc. Advanced Microelectronics Technology Division, Redondo Beach, California Section Manager responsible for starting up a GaAs pilot line, selecting capital equipment and Developed/transferred process technologies for MESFET, HEMT and HBT devices from R&D to pilot line. Process technology in Photolithography/Plasma Etch/PVD/CVD/Materials/Packaging

1984 to 1987 Honeywell Inc. Opto-electronics Division, Richardson, Texas

Senior Process Development Engineer for Photolithography, Plasma Etch, PVD, CVD for III-V III-V based GaAs IC device. Responsible for starting-up GaAs wafer pilot line, capital equipment selection, packaging/ assembly and testing. Front end/ back end process technology development- developed and transferred process/device technologies from R&D to pilot line for manufacturing.

Education

Ph.D. in Materials Sciences & Engineering

January, 1984. Cornell University, Ithaca, New York. B.S. in Materials Science and Engineering. June, 1978. National Tsing-Hua University, Hsin-Chu, Taiwan.

Personal data

Excellent communication, presentation and analytical skills, willingness to travel for applications

/product management/alliance management for advanced technologies. Citizenship: U.S. Citizen.



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