Office Project

OBJECTIVE:

Topursueachalengingcareerandtobeapartofprogressive

organizationthatgivesascopetoenhancemyknowledgeand utilizingmyskilstowardsthegrowthoftheorganization. EDUCATION:

BachelorofEngineeringinElectronicsand

Telecommunication-2018

73% (JaihindColegeofEngineering,Kuran,PuneUniversity) DiplomaElectronicsandTelecommunication-2015

81.12%(JaihindColegeofEngineering,Kuran)

SSC-2012

79.09%(G.R.P.SabnisVidyamandir,Narayangaon)

EXPERIENCE:

CompanyName:BitMapperIntegrationTechnologies

Pvt.Ltd,Pune.

Designation:HardwareDesignEngineer

Duration:Dec2018-Nov2019

CTC-3LPA

PROJECTS:

TITLE:DESIGNOFVIRTEX7FPGABASEDHIGHDEFINATION

THERMALIMAGER

Brief:ThisincludesDigitalinterfaceslikeSRAMs,NORFLASH, EEPROM,BPIFLASH (forconfiguration),Ethernets,and

AnaloginterfaceslikeVideoDAC,Serializer.

Role:ProjectLeader.

TITLE:DESIGNOFARTIX7FPGABASEDINTERROGATORUNIT

FORIRDE.

Brief:Themainaim ofthisprojectistointerfacethecamera interfaceandACUUnitwithFPGAArtix7.Itconsistsof

Peripherals like DDR3,Ethernet,USB-UART,BPI flash, Optocoupler,IMX6QProcessor

Role:Power calculation,Power system design,Circuit designing,I/Ocalculation, IO-Mux Calculation on the basis ofcomponentselectionandinterfacing.

PersonalDetails:

Name:Ashlesha

RohidasWajage.

Address:Moshi,Pune

E-mailID:

ashleshawajage@gmail.c

om

Mob.No.:

+917*********

LanguagesKnown:

English,Hindi,Marathi.

Toolsand

Technologies-

ISEdesignsuite

ofXilinx.

AlegroPCB

Editor.

SignalIntegrity.

Power

estimation.

Length

Matching.

Goodknowledge

inhardware

architectureand

designcycle

flow.

Experiencein

memories

interfacesSRAM,

BPIFLASH.

PowerSupply

TITLE:DESIGNOFVIRTEX4FPGABASEDT2SL.

Brief:IthasperipheralslikeVirtex4 FPGA,ADC,Video

Interfaces,SRAM,MemoryFlash,EEPROM,Serialinterfaces etc.

Role:Ihave done IO planning,FPGA selection,power

calculation,powersystemdesign,interfacingofperipherals, testingofFPGAboard.

TITLE:GROUNDCHECKOUTUNIT.

Brief:Itusedtoconfirm thateverysubsystem functioning according to the technicalspecifications lay down.It consistsofperipheralsinMotherBoardlikeKintex7,SRAM, DDR3,andDMA.AndDaughtercardslikeLVTTLmodule,

LVDSmodule,USBmoduleandRS422module.

Role:TestinganddebuggingthroughVHDLcodes.

DECLARATION:

Iherebydeclarethattheinformationfurnishedaboveistrueasperbestofmy knowledge.

WajageAshleshaRohidas Date:

Achievements:

Activelyparticipatedin

JCON2018

International

Conferenceorganized

byJCOE,Kuranand

SavitribaiPhule,Pune

University.

Activelyparticipatedin

AVISHKAR2K17Zonal

levelResearch

Competitionorganized

byAISSMSCOE,Pune.

Secured2ndprizein

NATIONALLEVEL

TECHNO-FEST(Poster

Presentation)

organizedbyJCOE,

Kuran.

Contact this candidate